Phase locked loop using digital loop filter and digitally contro

Details Phase locked loop using digital loop filter and digitally contro Phase locked loop using digital loop filter and digitally contro

1996-09-06

1998-03-10

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 25, H03D 324

Patent

active

057270384

ABSTRACT:
A phase locked loop (10) with a phase detector (11), a digital loop filter (12), a digital controlled oscillator (13) and a divide-by-N circuit (14) generates a periodic signal which has a predetermined phase and voltage related to a reference clock signal. A phase and frequency detector (21) outputs an average of error between a feedback delay clock and a reference clock to the digital loop filter (12). The digital loop filter (12) processes the phase detector (11) output and the inband quantization noise utilizing a sigma delta converter. The digital loop filter (12) utilizes a non binary weight scheme to minimize the number of bits changing states. The digital controlled oscillator (13) generates a loop clock signal utilizing a plurality of digital programmable delay elements. A divide-by-N circuit (14) performs a divide by 2560.

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Riley, et al.; "Delta-Sigma Modulation in Fractional-N Frequency Synthisis"; IEEE Journal of Solid State Circuits; vol. 28, No. 5; pp. 553-559 (1993).

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