Phase-locked loop timing recovery circuit

Details Phase-locked loop timing recovery circuit Phase-locked loop timing recovery circuit

1994-10-21

1996-12-03

Chin, Wellington

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375230, 375232, 375233, 375355, H03H 730, H04L 700, H03D 324

Patent

active

055815855

ABSTRACT:
A timing recovery apparatus for recovering the timing from sparse timing information in multi-level or partial response codes. The timing recovery apparatus includes a switch for sampling an incoming line code signal according to a selectable sample rate, a feed forward equalizer for filtering the sampled signal, a decision feedback equalizer for cancelling intersymbol interference in the filtered signal and for recovering the timing in the sampled signal. The timing recovery circuit creates a phase correction signal in response to a signal received from the feed forward equalizer and thereby control the sample rate of the sample switch so that the signal-to-noise ratio at the node before the decision is maximized. The voltage controlled crystal oscillator may be controlled within a certain frequency range by using a second phase detector which compares the phase of the signal controlling the sampling of the incoming line code with a reference clock.

REFERENCES:
patent: 3798576 (1974-03-01), Torpie et al.
patent: 3931585 (1976-01-01), Barker et al.
patent: 3962637 (1976-06-01), Motley et al.
patent: 4071827 (1978-01-01), Koike et al.
patent: 4129748 (1978-12-01), Saylor
patent: 4303837 (1981-12-01), Ansaldi et al.
patent: 4456890 (1984-06-01), Carickhoff
patent: 4490688 (1984-12-01), Borras et al.
patent: 4494242 (1985-01-01), Ehrenbard et al.
patent: 4520489 (1985-05-01), Hogge, Jr.
patent: 4583234 (1986-04-01), Ramadan
patent: 4677647 (1987-06-01), Aoyagi
patent: 4694259 (1987-09-01), Carickhoff et al.
patent: 4791386 (1988-12-01), Shiga
patent: 4805191 (1989-02-01), Burch et al.
patent: 4815103 (1989-03-01), Cupo et al.
patent: 4862485 (1989-08-01), Guinea et al.
patent: 4896334 (1990-01-01), Sayar
patent: 4972442 (1990-11-01), Steierman
patent: 4975660 (1990-12-01), Svenson
patent: 5018166 (1991-05-01), Tjahjadi et al.
patent: 5048060 (1991-09-01), Arai et al.
patent: 5059924 (1991-10-01), JenningsCheck
patent: 5068628 (1991-11-01), Ghoshal
patent: 5119401 (1992-06-01), Tsujimoto
patent: 5159291 (1992-10-01), Ghoshal
patent: 5181228 (1993-10-01), Takatori
patent: 5214671 (1993-05-01), Nakai
patent: 5297165 (1994-03-01), Ueda et al.
patent: 5325400 (1994-06-01), Co et al.
patent: 5353312 (1994-10-01), Cupo et al.
patent: 5388127 (1995-02-01), Scarpa
Gardner, Floyd M., Phaselock Techniques, 2nd Edition (John Wiley & Sons).
Best, Roland E., Phase--Locked Loops: Theory, Design, & Applications, "Theory of the Digital PLL", (McGraw Hill 1984).

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