Phase locked loop (PLL) with linear parallel sampling phase dete

Details Phase locked loop (PLL) with linear parallel sampling phase dete Phase locked loop (PLL) with linear parallel sampling phase dete

1997-06-19

2000-02-15

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375375, 375374, 375354, 331 11, 327 12, H03D 324

Patent

active

06026134&

ABSTRACT:
A parallel sampling phase detector with linear output response is disclosed. The parallel sampling phase detector for use in data recovery. The device includes a voltage controlled oscillator (VCO) that generates ten separate phase signals using a five stage ring oscillator. Five linear phase detectors are employed in the device, each operating during one of five "window" intervals. The "window" intervals are non-overlapping, and are generated using preselected ones of the VCO output phases. The linear phase detectors each generate, respectively, a variable pulsewidth pump up signal wherein the pulsewidth of the pump up signal is proportional to a phase difference between the input data signal applied to the phase detector, and the output phase signals of the VCO. Each phase detector also generates a pump down signal that has a fixed pulsewidth. A loop filter determines the difference between the pump up and pump down signals and develops a control signal to vary the output frequency and phase of the VCO in accordance therewith. Each phase detector also operates as a deserializer, capturing, during the interval when the respective "window" signal is active, the data signal from the input data stream. The plurality of sampled data signals are captured by a data register, which then outputs an n-bit (5-bit) parallel format data word. The linear phase detector includes means for generating the pump down signal in response to the generation of the pump up signal.

REFERENCES:
patent: 4535459 (1985-08-01), Hogge, Jr.
patent: 5548251 (1996-08-01), Chou et al.
patent: 5550515 (1996-08-01), Liang et al.
patent: 5633899 (1997-05-01), Fiedler et al.
patent: 5663688 (1997-09-01), Delmas et al.
patent: 5754080 (1998-05-01), Chen et al.
"A 0.8.mu.m CMOS 2.5Gb/s Oversampled Receiver for Serial Links;" Chih-Kong Ken Yang, Mark A. Horowitz; Feb. 9, 1996; 200-201, 158-159, 410.
"A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-Emphasis;" Alan Fiedler, Ross Mactaggart, James Welch, Shoba Krishnan; Feb. 7, 1997; 238-239, 186-187, 420.
"A 1.25Gb/s, 460mW CMOS Transceiver for Serial Data Communication;" Dao Long Chen, Michael O. Baker; Feb. 7, 1997; 242-243, 190-191, 422.
"A0.8-.mu.m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links;" Chih-Kong Ken Yang and Mark A. Horowitz; Dec. 1996; 2015-2023.

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