Phase locked loop (PLL) method and architecture

Details Phase locked loop (PLL) method and architecture Phase locked loop (PLL) method and architecture

2007-01-03

2010-02-16

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000, C327S148000, C327S155000, C327S157000, C375S371000, C375S372000, C375S373000, C375S374000, C375S375000, C375S376000, C331S017000

Reexamination Certificate

active

07663415

ABSTRACT:
A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.

REFERENCES:
patent: 4864253 (1989-09-01), Zwack
patent: 5896068 (1999-04-01), Moyal
patent: 6895525 (2005-05-01), Wilkie et al.
patent: 7180377 (2007-02-01), Leong et al.
patent: 2002/0196060 (2002-12-01), Ichimaru
patent: 2005/0226357 (2005-10-01), Yoshimura

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