Phase-locked loop (PLL) circuit containing a sampled phase...

Details Phase-locked loop (PLL) circuit containing a sampled phase... Phase-locked loop (PLL) circuit containing a sampled phase...

1998-01-28

2001-04-24

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C331S017000, C331S025000

Reexamination Certificate

active

06222895

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to phase-locked loop (PLL) circuits, and more particularly, to phase-locked loop (PLL) circuits containing a sampled phase detector.
BACKGROUND OF THE INVENTION
Phase-locked loop (PLL) circuits are frequently utilized to lock an oscillator in phase with a reference signal. PLL circuits are often utilized within receivers in digital communication systems to generate a local clock signal that is phase aligned with an incoming reference signal. The phase aligned local clock signal facilitates the receipt and processing of data sent by a transmitter in the communication system.
A conventional PLL circuit includes a phase detector, a filter and a voltage-controlled oscillator (VCO). In the conventional PLL circuit, the phase detector compares the incoming reference signal and the output of the VCO. The phase detector generates an error signal that is representative of the phase difference of the reference signal and the VCO output. The error signal is filtered and applied to the control input of the VCO to produce an output signal that tracks the phase of the reference signal.
Recently, a parallel receiver architecture has become popular in many digital communication systems. The parallel receiver recovers the clock from the incoming data sequence, typically using a PLL circuit. For a detailed discussion of a parallel receiver architecture and clock recovery, respectively, see T. H. Hu, P. R. Gray, “A Monolithic 480 Mb/s Parallel AGC/Decision/Clock-Recovery Circuit in 1.2-&mgr;m CMOS,” I.E.E.E. J. of Solid-State Circuits, Vol. 28, No. 12, 1314-20 (1993) and J. D. H. Alexander, “Clock Recovery From Random Binary Signals,” Electr. Lett., Vol. 11, No. 22, 541-42 (Oct. 1975), each incorporated by reference herein. Generally, the phase detector of a parallel receiver phase-locked loop (PLL) is frequently implemented as a sampled binary phase detector (SBPD).
A potential problem exists, however, for a PLL circuit based on a sampled binary phase detector (SBPD). Specifically, conventional sampled phase detectors generate a continuous charge output signal over the entire clock cycle to minimize the phase difference between the reference signal and the VCO output. The continuous output current, however, introduces an average delay of one-half of the clock cycle between the phase detector and the voltage-controlled oscillator (VCO). This delay significantly contributes to the oscillation of conventional PLL circuits based on sampled phase detectors around a phase error equal to zero (0). Thus, the phase difference between the reference signal and the VCO output never goes to zero and continues to oscillate around zero. Such oscillation may occur in any sampled nonlinear phase detector, where the output signal is constant during a clock cycle. If the oscillation is severe enough, the incoming data signal can be sampled in the wrong bit period. In addition, any amount of oscillation degrades the bit error rate of a receiver.
SUMMARY OF THE INVENTION
A PLL circuit is disclosed that includes a sampled phase detector, a filter and a voltage-controlled oscillator (VCO). The sampled phase detector compares an incoming reference signal, V
ref
, and the output of the VCO, V
O
, and generates an error signal, I
err
, representing the phase difference between the reference signal, V
ref
, and the VCO output, V
O
. The error signal, I
err
, is filtered by a low pass filter and applied to the VCO to produce an output signal, V
O
, that tracks the phase of the reference signal, V
ref
.
According to one aspect of the present invention, delay is reduced by replacing the continuous charge-pump current produced over an entire clock cycle by a conventional sampled phase detector with shorter current pulses of similar charge, thereby reducing jitter. The sampled phase detector injects all the charge-pump charge into the loop filter at once, reducing the effective delay by up to a half period.
According to another aspect of the present invention, the total delay in the feedback loop is reduced by applying a charge output current, I
err
, that is known to be required for a predefined number of clock cycles. PLL circuits based on sampled phase detectors typically produce a phase error that oscillates around zero. Thus, an additional charge injection can be applied to the VCO each time the phase error value is crossing zero, for the anticipated oscillation period until the next zero crossing. For example, when the phase error changes sign from negative to positive, it is known that a positive current will be injected into the low pass filter for several cycles (until the next zero crossing from positive to negative phases error), in order to adjust the phase of the VCO output, V
O
. Thus, the PLL circuit in accordance with the present invention generates a positive phase step that is applied to the VCO. In various embodiments, the phase step can be applied with or without a corresponding change to the frequency. All of the charge current, I
err
, is injected into the low pass filter for the estimated duration of the oscillation period, until the next zero crossing is predicted to occur. If the duration of the oscillation period is underestimated, the sampled phase detector will continue normal processing for the additional clock cycles until the next zero crossing is detected. If the duration of the oscillation period is overestimated, thereby initially injecting charge current for too many clock cycles, the next zero crossing will be passed, and the sampled phase detector will continue normal processing for the additional clock cycles until the second zero crossing is detected.


REFERENCES:
patent: 4535459 (1985-08-01), Hogge, Jr.
patent: 4562411 (1985-12-01), O'Rourke et al.
patent: 5448598 (1995-09-01), Yousefi et al.
patent: 5699387 (1997-12-01), Seto et al.
patent: 5926041 (1999-06-01), Duffy et al.
patent: 5945855 (1999-08-01), Momtaz
patent: 6005425 (1999-12-01), Cho
T.H Hu, P. R. Gray, “A Monolithic 480 Mb/s Parallel AGC/Decision/Clock-Recovery Circuit in 1.2&mgr;m CMOS,” IEEE J of Solid State Circuits, Vol. 28 No. 12, 1314-20 (1993).*
J.D.H. Alexander, “Clock Recovery from Random Binary Signals,” Electronic Letters, vol. 11 No. 22, 541-42 (Oct. 1975).

Affiliated with

Also associated with

Rating

Phase-locked loop (PLL) circuit containing a sampled phase... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase-locked loop (PLL) circuit containing a sampled phase..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop (PLL) circuit containing a sampled phase... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2538826