Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-03-03
1999-02-02
Ghebretinsae, Temesghen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375229, 327147, H03D 324
Patent
active
058675442
ABSTRACT:
In a first phase-locked loop, a digital value corresponding to the mean frequency of an input clock signal is obtained. In a second phase-locked loop, the mean value of the phase difference of an output clock relative to the input clock is measured and is added to the digital value corresponding to the mean frequency, to obtain a control value. From this control value, a control signal for uniformly controlling a dual-modulus frequency divider is generated and supplied to the dual-modulus frequency divider. In a moving-average circuit, a selector selects input data when updating the contents of a serial latch circuit array, and selects an output of the serial latch circuit array when accumulating values. Values serially output from the latch circuit array for accumulation are successively added up using an adder and a latch circuit. In a division-ratio equalization circuit, a calculating circuit calculates quotients a.sub.0, a.sub.1, a.sub.2 . . . a.sub.m when the control value is expressed as 1/(a.sub.0 +1/(a.sub.1 +1/(a.sub.2 + . . . +1/a.sub.m)) . . . ), and the quotients are set as division ratios in programmable frequency dividers connected in cascade, through which a reference clock signal is frequency-divided to obtain the control signal.
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Electronics and Communications in Japan, vol. 73, No. 4, 1 Apr. 1990, New York, US, pp. 48-55, XP000149326, T. Inoue et. al., "Interference Suppression Using DPLL with Notch Frequency Characteristic", p. 49, col. 2, line 1--p. 50, col. 2, line 22; figure 1.
Fujitsu Limited
Ghebretinsae Temesghen
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