Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
1999-10-15
2001-05-15
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S288000, C327S276000, C327S261000, C327S158000, C327S525000
Reexamination Certificate
active
06232813
ABSTRACT:
RELATED APPLICATION
This application is related to Korean Application No. 98-43714, filed Oct. 19, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices containing phase locked loops and methods of operating same.
BACKGROUND OF THE INVENTION
Many integrated circuit devices (e.g., memory devices) operate in-sync with externally supplied clock signals by generating one or more internal clock signals that are preferably phase locked with the external clock signal and with each other. As will be understood by those skilled in the art, accurate phase locking of clock signals can be especially important for integrated circuit devices that operate a high frequencies. Such integrated circuit devices may include merged memory with logic (MML) devices, Rambus DRAM devices and double data rate synchronous DRAM devices (DDR-SDRAM).
Conventional techniques for providing clock signals across a relatively large integrated circuit chip typically suffer from an inability to accurately match clock signal phase, since clock signals traversing different length signal paths experience different signal delays (e.g., RC delays). These nonuniform delays make it difficult to accurate maintain synchronization of all devices on an integrated circuit chip. To address these limitations, many delay locked loop (DLL) integrated circuits generate advanced clock signals to compensate for the delays associated with signal path traversal. For example,
FIG. 1
illustrates a conventional delay locked loop integrated circuit
10
that generates an advanced clock signal ADCLKD. This delay locked loop integrated circuit
10
includes a phase detector
12
, a charge pump
14
, a variable delay circuit
16
and a delay compensation circuit
18
. The phase detector
12
receives a reference clock signal RCLK and a feedback clock signal (output on signal line
21
by the delay compensation circuit
18
) and generates a pair of phase detected signals on signal lines
13
a
and
13
b
. These phase detected signals are provided to the charge pump
14
which generates a phase control signal (VCON
1
). This phase control signal VCON
1
may have a magnitude that is proportional to a phase difference between the reference clock signal RCLK and the feedback clock signal.
The variable delay circuit
16
generates the advanced clock signal ADCLKD as a delayed version of the reference clock signal RCLK. As illustrated by
FIG. 2
, which is a block diagram of the variable delay circuit
16
of
FIG. 1
, the degree to which the advanced clock signal ADCLKD is delayed in time or phase relative to the reference clock signal RCLK is a function of the number of delay stages ST1−STn and the delay provided by each stage. As will be understood by those skilled in the art, the delay provided by each stage may be a function of the magnitude of the phase control voltage VCON
1
.
Unfortunately, the degree to which the delay provided by the variable delay circuit
16
of
FIGS. 1-2
can be varied is limited by the fixed number of delay stages and the limited degree to which the delay of each stage can be varied in response to variations in the magnitude of the phase control signal VCON
1
. Such limited delay variation can increase the likelihood that the phase locked loop will experience jitter when high frequency and low frequency reference clock signals RCLK are used. Moreover, limited delay variation may make it difficult to control the timing and phase of such advanced clock signals to exactly match the delays associated with signal path traversal.
Thus, notwithstanding the delay locked loop integrated circuit of
FIGS. 1-2
, there continues to be a need for improved phase locked loop integrated circuits having greater signal frequency bandwidth and other improved characteristics.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved phase locked loop integrated circuits and methods of operating same.
It is another object of the present invention to provide phase locked loop integrated circuits having wide signal frequency bandwidth and methods of operating same.
It is still another object of the present invention to provide phase locked loop integrated circuits that can generate advanced clock signals having carefully controlled phase relationships and methods of operating same.
These and other objects, advantages and features of the present invention are provided by delay locked loop integrated circuits that preferably include a phase detector, a charge pump, a variable delay circuit and a delay compensation circuit. The phase detector receives a pair of periodic signals. These periodic signals may include a reference clock signal (e.g., RCLK) and a feedback clock signal (e.g., FDCLK). The phase detector compares the phase of the reference clock signal relative to the feedback clock signal and generates a pair of phase detected signals that each have a first property (e.g., pulse width) that is proportional to a difference in phase between the reference clock signal and the feedback clock signal. The charge pump performs the function of converting the pair of phase detected signals into a phase control signal (e.g., VCON
2
) having a magnitude proportional to the first property of the at least one of the phase detected signals.
The variable delay circuit receives the reference clock signal and the phase control signal and generates an advanced clock signal (e.g., ADCLKN) having a phase that leads the reference clock signal by an amount determined by the overall delay provided by the variable delay circuit. This advanced clock signal can be provided to other integrated circuit devices (e.g., memory devices) which may need to operate in-sync with the reference clock signal. Here, the advanced phase of the advanced clock signal relative to the reference clock signal can account for the timing skew or delay associated with providing the advanced clock signal to other devices and/or remote portions of an integrated circuit substrate. The delay compensation circuit may also add an additional fixed delay to the advanced clock signal. In particular, the sum of the delay provided by the delay compensation circuit and the variable delay circuit is preferably set at a value equal to an integer multiple of the period (T) of the reference clock signal, so that the feedback clock signal will be in-phase with the reference clock signal.
To meet these timing requirements, the delay provided by the variable delay circuit can be variably adjusted using preferred fuse-enabled and fuse-disabled delay stages. The fuse-disabled delay stage comprises a unit delay device and a disable control circuit having a disable fuse therein. The disable control circuit includes: a disable signal generating circuit, an output transmission gate electrically connected between an output of the unit delay device and an output of the fuse-disabled delay stage, an input transmission gate electrically connected between an input of the fuse-disabled delay stage and an input of the unit delay device; and a bypass transmission gate electrically connected between the input of the fuse-disabled delay stage and the output of the fuse-disabled delay stage. The fuse-enabled delay stage is similarly constructed and includes an enable fuse therein. Based on a preferred aspect of the present invention, one or more disable fuses or enable fuses within the variable delay circuit can be cut so that the overall delay provided by the variable delay circuit can be decreased or increased to establish a desired phase difference between the reference clock signal and the advanced clock signal. Preferred methods of operating phase locked loop integrated circuits are also provided by the present invention.
REFERENCES:
patent: 4749961 (1988-06-01), Kato et al.
patent: 4789996 (1988-12-01), Butcher
patent: 4873491 (1989-10-01), Wilkins
patent: 5229752 (1993-07-01), Gliebe et al.
patent: 5336939 (1994
Le Dinh T.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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