Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-08-31
2001-12-11
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S237000
Reexamination Certificate
active
06329854
ABSTRACT:
RELATED APPLICATION
This application is related to Korean Application No. 98-36094, filed Sep. 2, 1998, the disclosure of which is hereby incorporated herein by reference.
1. Field of the Invention
The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices containing phase locked loops and methods of operating same.
2. Background of the Invention
Many integrated circuit devices (e.g., memory devices) operate in-sync with externally supplied clock signals by generating one or more internal clock signals that are preferably phase locked with the external clock signal and with each other. As will be understood by those skilled in the art, accurate phase locking of clock signals may be especially important for integrated circuit devices that operate a high frequencies.
FIG. 1
illustrates a conventional phase locked loop integrated circuit that includes a phase detector
110
, a charge pump circuit
130
, a voltage controlled delay line (VDL)
150
, and a compensation delay device
170
that provides a fixed delay. The phase detector
110
compares the phase of an external clock signal CLK against an internal clock signal PCLK and generates a phase detected signal (PDS) at an output thereof. The phase detected signal PDS may have a pulse width proportional to the magnitude of the phase difference between the external clock CLK and internal clock PCLK. The charge pump circuit
130
may also perform the function of generating a phase control signal VCON in response to the phase detected signal PDS. In particular, the charge pump circuit
130
may perform the function of increasing the magnitude of the phase control signal VCON in response to an increase in the pulse width of the phase detected signal PDS and vice versa.
As illustrated, the voltage controlled delay line (VDL)
150
comprises a plurality of unit delay devices
151
-
154
and generates a delayed version of the external clock signal CLK as signal DCLK. In particular, signal DCLK is out-of-phase relative to the external clock signal by a delay equal to the sum of the delays provided by the unit delay devices
151
-
154
. The delay provided by each of these unit delay devices
151
-
154
may vary depending on the magnitude of the phase control signal VCON. For example, the individual delays provided by the unit delay devices
151
-
154
may decrease with increases in the magnitude of the phase control signal VCON. The delay provided by the voltage controlled delay line
150
may therefore automatically decrease as the phase difference (&phgr;) between the internal clock signal PCLK and the external clock signal CLK increases in response to an increase in the frequency of the external clock signal CLK. Alternatively, the delay provided by the voltage controlled delay line
150
may automatically increase as the phase difference (&phgr;) between the internal clock signal PCLK and the external clock signal CLK decreases (e.g., becomes more negative) in response to a decrease in the frequency of the external clock signal CLK.
Unfortunately, because the delay-voltage characteristics of the unit delay devices
151
-
154
may be non-linear (and may also saturate at high and low VCON), the overall delay provided by the voltage controlled delay line
150
may not have symmetric low frequency and high frequency characteristics (i.e., the change in delay/change in voltage at large VCON may not be the same as the change in delay/change in voltage at small VCON). Moreover, once the number of unit delay devices in the voltage controlled delay line
150
is fixed at a predetermined number, the operating frequency range of the integrated circuit become similarly fixed.
Thus, notwithstanding the above-described phase locked loop integrated circuit, there continues to be a need for improved phase locked loop integrated circuits having greater signal frequency bandwidth and other improved characteristics.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved phase locked loop integrated circuits and methods of operating same.
It is another object of the present invention to provide phase locked loop integrated circuits having wide signal frequency bandwidth and methods of operating same.
It is still another object of the present invention to provide phase locked loop integrated circuits that can adjust dynamically to input signals having varying frequencies and methods of operating same.
It is yet another object of the present invention to provide phase locked loop integrated circuits that have reduced susceptibility to signal jitter and methods of operating same.
These and other objects, advantages and features of the present invention are provided by delay locked loop integrated circuits that preferably include a phase detection circuit, a variable delay device and a delay control circuit. The variable delay device and delay control circuit provide improved characteristics by increasing the signal frequency bandwidth of the delay locked loop integrated circuit in a preferred manner. The phase detection circuit is configured to perform the functions of comparing first and second periodic signals and generating a phase control signal (e.g., VCON) having a first property (e.g., magnitude) that is proportional to a difference in phase between the first and second periodic signals. These first and second periodic signals may be an external clock signal CLK and an internal clock signal PCLK, respectively. The magnitude of the phase control signal VCON may be controlled to increase as the phase difference between the external clock signal CLK and internal clock signal PCLK increases and decrease as the phase difference decreases.
The phase detection circuit may comprise a phase detector that receives the external clock signal CLK and the internal clock signal PCLK and generates a phase detected signal (PDS). The phase detected signal PDS may have a pulse width proportional (e.g., directly proportional) to the difference in phase between the external clock signal CLK and the internal clock signal PCLK. The phase detection circuit may also comprise a charge pump circuit that generates the phase control signal VCON in response to the phase detected signal PDS. The charge pump circuit may perform the function of increasing the magnitude of the phase control signal VCON in response to an increase in the pulse width of the phase detected signal PDS.
The delay control circuit is responsive to the phase control signal VCON and generates a delay control signal that is provided to the variable delay device. The delay control circuit may comprise a counter that generates a control clock signal in response to the internal clock signal PCLK. The delay control circuit also preferably comprises a first comparator, a second comparator and a shift register. The first comparator compares the phase control signal VCON against a “high” first property (e.g., magnitude) threshold (VREFH) and the second comparator compares the phase control signal VCON against a “low” first property (e.g., magnitude) threshold (VREFL). The output of the first comparator is electrically connected to a DOWN signal line and the output of the second comparator is electrically connected to an UP signal line. Based on a voltage comparison, the DOWN signal line is driven to a logic 1 level whenever the magnitude of the phase control signal VCON is greater than VREFH and is held at a logic 0 level whenever the magnitude of the phase control signal VCON is less than VREFH. Alternatively, the UP signal line is driven to a logic 1 level whenever the magnitude of the phase control signal VCON is less than VREFL and is held at a logic 0 level whenever the magnitude of the phase control signal VCON is greater than VREFL. Based on this configuration of the first and second comparators, the UP and DOWN signal lines are both held at logic 0 levels whenever the magnitude of the phase control signal VCON is within a predetermined range (i.e., VREFL≦VCON≦VREFH). The “width” of this range is preferably d
Lee Jae-hyoong
Lee Sang-Bo
Le Dinh T.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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