Phase locked loop having enhanced locking characteristics

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S148000, C331S034000

Reexamination Certificate

active

11247938

ABSTRACT:
A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

REFERENCES:
patent: 5075640 (1991-12-01), Miyazawa
patent: 5278522 (1994-01-01), Atriss et al.
patent: 5374904 (1994-12-01), Ishibashi
patent: 5963058 (1999-10-01), Thomas
patent: 6028488 (2000-02-01), Landman et al.
patent: 6308055 (2001-10-01), Welland et al.
patent: 6414535 (2002-07-01), Ooishi
patent: 6842082 (2005-01-01), Tan
patent: 10 2005 058 137 (2006-06-01), None
patent: 2004-120215 (2004-04-01), None
patent: 100272524 (2000-08-01), None
patent: 1020030054196 (2003-07-01), None
Young et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range of Microprocessors,” IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.
Office Action, German Application No. 10 2005 063 232.7-35, Feb. 26, 2007.

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