Phase-locked loop having dynamically adjustable up/down...

Details Phase-locked loop having dynamically adjustable up/down... Phase-locked loop having dynamically adjustable up/down...

2008-07-22

2008-07-22

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000, C713S503000

Reexamination Certificate

active

07404099

ABSTRACT:
According to embodiments of the present invention, a phase-locked loop (PLL) may include circuitry to select a wide pulse width for the phase-frequency detector control signal when the PLL is in a frequency acquisition stage, a narrow pulse width for the phase-frequency detector control signal when the PLL is in a phase capture stage, and a wide pulse width of the phase-frequency detector control signal when the PLL is in a lock stage.

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patent: 2006/0022757 (2006-02-01), Jung
patent: PCT/US2005/025814 (2005-11-01), None

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