Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1997-02-25
1999-10-19
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375374, H03D 324
Patent
active
059701064
ABSTRACT:
A digital phase locked loop (PLL) comprises a phase/frequency comparator block including a comparator for comparing a reference signal with an internal clock signal obtained by dividing an output clock signal of the PLL circuit. The phase/frequency comparator supplies a two-bit signal, either one of the bits having a pulse width based on the difference between the phases or frequencies of the reference signal and internal clock signal. The two-bit signal is amplified by a CMOS latch amplifier during a sense enable cycle of the amplifier to be supplied to a digital controller, which in turn controls a voltage controlled oscillator via a D/A converter. The digital PLL circuit executes frequency acquisition and phase acquisition in a single mode to simplify the circuit configuration.
REFERENCES:
patent: 5386437 (1995-01-01), Yasuda
patent: 5563921 (1996-10-01), Mesuda et al.
patent: 5610954 (1997-03-01), Miyashita
patent: 5666388 (1997-09-01), Neron
Dunning et al. (1995) "An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microoprocesors" EEICE Trans. Electron. vol. E78-C: 660-670.
Chin Stephen
NEC Corporation
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