Phase locked loop for stable clock generation in...

Details Phase locked loop for stable clock generation in... Phase locked loop for stable clock generation in...

2001-01-24

2003-04-01

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S011000, C331S025000, C331S175000, C327S157000, C327S159000, C369S047360

Reexamination Certificate

active

06542041

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an optical system, and more particularly, to a phase locked loop for stable clock generation in applications of wide band channel clock recovery, and an operation method thereof.
2. Description of the Related Art
Generally, an optical system employs a phase locked loop (PLL) for bit clock generation. In the operation of the PLL, a static phase error is essential to clock generation. The static phase error indicates a state in which the phases of two input signals are different even in the case where the input signals are frequency-locked. When an optical instrument reads data recorded on an optical disc using a servo system of a constant angular velocity (CAV), the frequency of a voltage controlled oscillator (VCO) changes by a factor of 1.5 while a pickup moves from the innermost part to the outermost part of the optical disc. Accordingly, the control voltage of the VCO should be continuously changed. However, as the VCO control voltage changes in a conventional PLL, the threshold voltage does not change, thereby causing an error. This error is referred to as a static phase error. Since a bit error rate (BER) can be momentarily changed depending on the static phase error, the static phase error is considered as an essential factor. When current mismatching occurs between a PMOS transistor constructing a current source and an NMOS transistor constructing a current sink in the charge pump of the PLL, a current offset may occur. Accordingly, a phase error may occur at the point of change in current. In other words, the static phase error occurs due to a difference between the frequency responses of transistors operating as switching devices of the charge pump.
Conventionally, a technique for addressing the issue of a varying BER uses the characteristic of a VCO control voltage, i.e., low-pass filtered direct current voltage, changing when a static phase error occurs. In this method, when the low-pass filtered direct current voltage changes, the variation of the low-pass filtered direct current voltage is detected by an error amplifier and a threshold detector. Accordingly, a VCO is compensated for by a voltage corresponding to the variation caused by the static phase error through a digital-to-analog converter. In other words, when a conventional PLL has a wide frequency band, a VCO control voltage changes so that a threshold essential to control cannot be detected. Alternatively, when using a conventional method of detecting a threshold, a VCO voltage changes and is offset from a center voltage. Then, in a charge pump, the charging current is different from the discharging current so that a regular static phase error cannot be obtained.
For these reasons, the conventional method using a VCO control voltage cannot be applied to the CAV mode widely used in optical systems. In other words, since the VCO control voltage always changes in the CAV mode, it cannot be determined whether the change in voltage is due to a static phase error or due to CAV control. Accordingly, the conventional method described above is restrictively applied only to clock synthesis applications or to the constant linear velocity (CLV) of an optical instrument.
SUMMARY OF THE INVENTION
To address the above limitations, it is an object of the present invention to provide a phase locked loop for stable clock generation in applications of wide band channel clock recovery, in which a clock signal can be stably regenerated with respect to a static phase error when an optical system operates at a constant angular velocity.
It is another object of the present invention to provide a static phase error control method performed in the phase locked loop.
Accordingly, to achieve one object of the invention, there is provided a phase-locked loop (PLL) performing frequency detection and phase detection with respect to an eight to fourteen modulation (EFM) signal and a PLL clock signal and adjusting the current based on the results of the frequency detection and the phase detection, thereby generating the PLL clock signal synchronized with the EFM signal. The PLL includes a charge pump, a first low-pass filter, a voltage controlled oscillator and a static phase error controller. The charge pump sources or sinks the current in response to the results of the frequency detection and the phase detection and outputs the result of sourcing or sinking the current. The first low-pass filter low-pass filters the signal output from the charge pump and outputs the filtered result as a direct current control voltage. The voltage controlled oscillator receives the control voltage and a predetermined reference voltage by way of differential input, converts a voltage into a current, and delays an oscillation output signal based on the converted current, thereby generating the PLL clock signal. The static phase error controller compares the control voltage with a triangular signal having a predetermined period and a predetermined amplitude and changes the reference voltage based on the compared result.
To achieve the other object of the invention, there is provided a method of controlling a static phase error in a phase locked loop (PLL) including a charge pump for adjusting the amount of current in response to the results of performing frequency detection and phase detection with respect to an eight to fourteen modulation (EFM) signal and a PLL clock signal, and a voltage controlled oscillator for generating the PLL clock signal in response to a direct current control voltage corresponding to the adjusted amount of the current and in response to a predetermined reference voltage. First, in step (a), it is determined whether the control voltage changes in a predetermined operating mode. In step (b), the control voltage is adjusted in the opposite direction to the change of the control voltage when it is determined that the control voltage changes. In step (c), it is determined whether the control voltage is at a center voltage after the step (b). In step (d), the PLL clock signal corresponding to the control voltage is generated when it is determined that the control voltage is at the center voltage. In step (e), the EFM signal and the PLL clock signal are received, and frequency detection and phase detection are performed with respect to them.


REFERENCES:
patent: 5121086 (1992-06-01), Srivastava
patent: 6229362 (2001-05-01), Choi

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