Phase locked loop for reducing electromagnetic interference

Details Phase locked loop for reducing electromagnetic interference Phase locked loop for reducing electromagnetic interference

2002-09-24

2004-03-09

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S018000, C331S010000, C331S025000, C327S159000

Reexamination Certificate

active

06703902

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase locked loop (PLL), and more particularly, to a PLL for reducing electromagnetic interference (EMI).
2. Description of the Related Art
A phase locked loop (PLL) plays a vital role in reducing electromagnetic interference (EMI) in digital systems. As technology continues to develop, digital systems need to be able to support high speeds and high density. PLLs included in such digital systems are no exception to the high-speed trend. However, the high speeds of the digital systems and the PLL may cause EMI which is generated when the energy of a high frequency signal exceeds a predetermined reference value. In particular, semiconductor devices are very sensitive to EMI.
A simple method of reducing EMI is by modulating the frequency of a reference signal having a high energy, i.e., a high power, at a certain frequency into a frequency signal having a lower energy. For example, if the frequency of the reference signal is 1 MHz, the frequency of the reference signal is modulated to be between 0.99 MHz and 1.01 MHz over a pre-defined repetitive cycle. That is, the frequency of the PLL output signal is modulated into the frequency signal between the maximum frequency and the minimum frequency allowed by the system using the PLL output signal, repeatedly at a pre-defined interval.
FIG. 1
is a graph showing modulation frequency and modulation rate.
With reference to
FIG. 1
, a frequency-modulated signal varies between a maximum frequency (1+&dgr;) F
0
and a minimum frequency (1−&dgr;) F
0
over an interval of 1/Fm. Here, F
0
is the reference frequency. The modulation frequency Fm and the frequency rate &dgr; can be determined randomly. It is preferable that the modulation frequency Fm be between 30 KHz and 100 KHz and the modulation rate &dgr; be 4% or less.
FIG. 2
illustrates a modulated signal whose sinusoidal profile is shown in (a) and whose spectrum is shown in (b), a modulated signal whose triangular profile is shown in (c) and whose spectrum is shown in (d), and a modulated signal whose profile, which resembles that of Hershey Kisses as patented by Lexmark, Inc., is shown in (e) and whose spectrum is shown in (f).
In case of the modulated signal profile having the sinusoidal profile of (a), the power is too high at the sides, as shown in (b) to be used. Therefore, the modulated signals having the triangular profile or Hershey Kisses profile are used.
A dithered PLL or a spread spectrum clock generator (SSCG), is a device used to reduce EMI by modulating the frequency and reducing the power gain. The SSCG is the patented technology of Lexmark and is called a dithered PLL. The modulation methods include center spreading, up spreading and down spreading.
FIG. 3
shows the spectrums of the dithered PLL power corresponding to different spreading methods.
FIG. 3
shows reference signals and spectrums in (a), (c), and (e of the signals generated as a result of the modulation of the reference signals and profiles in (b), (d), and (f) of the modulated signals. Graphs (a) and (b) illustrate center spreading, graphs (c) and (d) illustrate up spreading, and graphs (e) and (f) illustrate down spreading.
With reference to
FIG. 3
, the above 3 spreading methods will be described in detail.
First, in the center spreading method shown in (a) and (b), a reference signal having a narrow frequency range and a high power peak at the center of (a) is modulated into a frequency signal having a broader frequency range and a lower power.
Second, in the up spreading method shown in (c) and (d), a reference signal having a narrow frequency range and a high power peak at the left side of (c) is modulated into a frequency signal having a broader frequency range and a lower power.
Third, in the down spreading method shown in (e) and (f), a reference signal having a narrow frequency range and a high power peak at the right side of (e) is modulated into a frequency signal having a lower frequency range and a lower power.
In the past, two methods were used to perform the above spreading. One was to control the least significant bit (LSB) of a divider, and the other was to carry a sawtooth waveform on the electric potential of a loop filter. For the first method, the SSCG adopting a read only memory (ROM) controller suggested by Hardin of Lexmark Inc. is used. Sigma delta can also be adopted. For the second method, a pulse generator is installed to load a sawtooth wave into the electric potential of the loop filter, which was suggested by Neomagic Inc.
In a case where the ROM controller is used, the above spreading is performed by ROM coding. Therefore, the data of the ROM needs to be newly coded in order to adjust the output frequency ranges. In addition, the ROM occupies too large a space in the semiconductor device. Installing the pulse generator to load a sawtooth wave into the electric potential of the loop filter limits how much the output frequency can be changed. As a result, a device, which is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control the modulation frequency and the modulation rate, is needed.
SUMMARY OF THE INVENTION
To solve the above problem, it is an objective of the present invention to provide a phase locked loop (PLL) for reducing electromagnetic interference (EMI), where the PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control the modulation frequency and the modulation rate.
The invention is directed to a PLL for reducing EMI. The PLL of the invention includes a pre-divider for generating a reference frequency signal by dividing the signal inputted to the PLL by a pre-defined value, a phase detector for receiving the reference frequency signal and a feedback signal, detecting the phase difference between the two signals, generating a control signal depending on the detected phase difference and outputting a control voltage generated as a result of processing of the control signal by a pre-defined process, a voltage controlled oscillator (VCO) for receiving the control voltage and multiple switching control signals, and outputting a first oscillation signal having a pre-defined frequency in response to the control voltage while outputting a second oscillation signal which is delayed by as much as n-times (where n is an integer) the basic delay time of the first oscillation signal, in response to the multiple switching control signals, a main divider for receiving the second oscillation signal and outputting the feedback signal that commands the increase or decrease of the frequency of the first oscillation signal, a modulation control block for receiving modulation frequency data, modulation rate data, the feedback signal, and the second oscillation signal, and outputting the multiple switching control signals, and a post-divider for receiving the first oscillation signal and outputting signals by dividing the first oscillation signal by a pre-defined value.
A PLL for reducing EMI according to a second embodiment of the present invention includes a phase detection and filter unit, a voltage-controlled oscillator (VCO), a phase interpolator, a modulation control block, and a main divider. The phase detection and filter unit compares the phase of a predetermined reference frequency signal with the phase of a predetermined feedback signal to generate a control voltage having a value variable according to the difference of phases. The VCO generates a first oscillation signal having a frequency variable in response to the control voltage and first through M
th
clock signals having frequencies variable in response to the control voltage. The phase interpolator receives the first through M
th
clock signals, divides the phase difference between two sequential clock signals of the first through M
th
clock signals in response to predetermined first through N
th
switching control signals, and generates a second oscillation signal having a frequ

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