Phase locked loop for high speed data capture of a serial data s

Details Phase locked loop for high speed data capture of a serial data s Phase locked loop for high speed data capture of a serial data s

1996-02-02

1997-05-27

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 1A, H03D 324

Patent

active

056338996

ABSTRACT:
A phase locked loop locks on to the phase of a high speed serial data stream. The phase locked loop includes a multiple bit latch, a multiple-stage voltage controlled oscillator, a phase detection circuit and a feedback circuit. The multiple-bit latch has a plurality of data latch elements and boundary-detect latch elements. Each latch element includes a latch input for receiving the serial data stream, a sample clock input and a latch output. The multiple-stage voltage controlled oscillator has a voltage control input, a plurality of sample clock outputs and an adjustable delay between each sample clock output. Each sample clock output is coupled to a corresponding sample clock input. The phase detection circuit is coupled to the latch outputs of the data and boundary-detect latch elements and has a phase control output. A feedback circuit is coupled between the phase control output and the voltage control input.

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