Phase-locked loop control circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C375S375000

Reexamination Certificate

active

10355516

ABSTRACT:
An electrical circuit is disclosed, which comprises a phase locked loop (PLL) circuit and a PLL start-up circuit configured to selectively provide a reference signal to the phase locked loop circuit based upon relative frequencies of an input signal to the phase locked loop circuit and an output signal of the phase locked loop circuit.Further, a method for controlling a phase locked loop circuit is disclosed, which comprises the step of selectively providing a reference signal to the phase locked loop circuit in response to relative frequencies of an input signal to the phase locked loop circuit and an output signal of the phase locked loop circuit.

REFERENCES:
patent: 4365211 (1982-12-01), Lee
patent: 4542351 (1985-09-01), Okada
patent: 4596963 (1986-06-01), Lawton et al.
patent: 4787097 (1988-11-01), Rizzo
patent: 5955928 (1999-09-01), Smith et al.
patent: 5982239 (1999-11-01), Takahashi et al.
patent: 6407600 (2002-06-01), Lu et al.
patent: 10013224 (1998-01-01), None

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