Phase-locked loop configuration

Details Phase-locked loop configuration Phase-locked loop configuration

1994-08-03

1995-11-28

Tse, Young

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375374, 326 95, 327158, 327160, 327161, H03L 706, H03K 5159, G06F 112

Patent

active

054715121

ABSTRACT:
A phase-locked loop configuration includes a controllable delay device having a signal path with at least one inverter having supply lines, at least one field effect transistor having a load path, and at least one capacitor connecting the load path transversely to the signal path. A phase detector receives a reference signal and receives an input signal through the delay device. A first controller is connected downstream of the phase detector for controlling the load path of the at least one field effect transistor in the delay device. At least one pair of further field-effect transistors has load paths connected into the supply lines of the at least one inverter. A second controller is connected downstream of the phase detector for controlling the load paths of the further field effect transistors.

REFERENCES:
patent: 4489342 (1984-12-01), Gollinger et al.
patent: 4806804 (1989-02-01), O'Leary
patent: 4899070 (1990-02-01), Ou et al.
patent: 5036528 (1991-07-01), Costantino et al.
patent: 5285483 (1994-02-01), Ogawa et al.
patent: 5319680 (1994-06-01), Port et al.
patent: 5363419 (1994-11-01), Ho
patent: 5375148 (1994-12-01), Parker et al.
IEEE Journal of Solid-State Circuits, vol. 21, No. 5 Oct. 1988 (Johnson et al.) pp. 1218-1223, "A Variable Delay Line PLL for CPU-Coprocessor Synchronization".
Australian Patent Abstract No. AU-A-24503/84, Backes et al., Aug. 23, 1984.

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