Phase-locked loop circuit with reduced jitter

Details Phase-locked loop circuit with reduced jitter Phase-locked loop circuit with reduced jitter

1999-02-17

2002-03-19

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S003000, C327S040000

Reexamination Certificate

active

06359948

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to logic circuits, and in particular to a phase-locked loop circuit with reduced jitter.
BACKGROUND OF THE INVENTION
Phase-locked loop (PLL) circuits are used for a variety of purposes, including signal demodulation, frequency synthesis, pulse synchronization of signals from mass storage devices, and regeneration of “clean” signals. A PLL circuit typically compares a variable-frequency signal to a reference signal to determine a frequency difference, which is then fed back to the variable-frequency signal generator to synchronize the two signals. Often, logic circuit elements such as frequency dividers are placed between at least one of the two signal sources and the frequency comparator. Each such intervening logic circuit element, known as a regenerator, has an uncertainty in its output signal timing and therefore contributes to an overall signal timing uncertainty in the PLL circuit, thereby contributing to jitter in the phase-locked loop.
To increase the versatility of a phase-locked loop circuit, it is desirable to introduce flexibility in the frequency divide ratios used to generate the signals used by the frequency comparator. This requires the introduction of multiplexers after the frequency dividers to select the signal with the desired frequency division ratio. These multiplexers are also regenerators, further contributing to the jitter of the phase-locked loop circuit.
SUMMARY OF THE INVENTION
Therefore, a need has arisen for a phase-locked loop circuit that addresses the disadvantages and deficiencies of the prior art. In particular, a need has arisen for a phase-locked loop circuit with selectable frequency divide ratios and reduced jitter.
Accordingly, an improved phase-locked loop circuit is disclosed. In one embodiment, the phase-locked loop circuit includes a variable-frequency oscillator that generates a first oscillator signal, a reference signal source that generates a second oscillator signal, a control block that generates a select signal, and a frequency divider that receives as an input signal one of the first and second oscillator signals. The frequency divider also receives the select signal from the control block. The frequency divider generates a plurality of frequency-divided signals in response to the input signal, and selects a selected one of the plurality of frequency-divided signals as an output signal in response to the select signal. The frequency divider also synchronizes its output signal to its input signal. The phase-locked loop also includes a frequency comparator that receives the output signal of the frequency divider and a signal derived from one of the first and second oscillator signals. The frequency comparator compares the output signal of the frequency divider to the signal derived from one of the first and second oscillator signals, and provides a feedback signal to the variable-frequency oscillator reflecting this comparison.
An advantage of the present invention is that, while a programmable frequency divider is used to maximize the flexibility of the phase-locked loop circuit, the number of regenerators introduced by the frequency divider is effectively limited to one, thereby reducing the jitter caused by the frequency divider.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and for further features and advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:
FIG. 1
is a block diagram of a phase-locked loop circuit constructed in accordance with the present invention;
FIG. 2
is a block diagram of one embodiment of a reference clock source for use in the phase-locked loop circuit; and
FIG. 3
is a block diagram of a frequency divider for use in the phase-locked loop circuit.


REFERENCES:
patent: 4087677 (1978-05-01), Dunn et al.
patent: 4590602 (1986-05-01), Wolaver
patent: 0 788 240 (1997-08-01), None
patent: 0 841 754 (1998-05-01), None
patent: 01 254021 (1989-10-01), None

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