Phase locked loop circuit having automatic range setting logic

Details Phase locked loop circuit having automatic range setting logic Phase locked loop circuit having automatic range setting logic

1996-04-18

1998-06-09

Vo, Don N.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 1A, 331DIG2, 327159, 327160, 327163, H03L 710

Patent

active

057647127

ABSTRACT:
A method for setting a locking frequency operating range of the phase locked loop (PLL) circuit and a phase locked loop (PLL) circuit are provided with range select logic for detecting an unknown reference clock frequency and for setting a locking frequency operating range of the phase locked loop. First a bypass mode for the phase locked loop (PLL) circuit is set. An unknown reference clock frequency is applied to a first counter. A known oscillator clock frequency is applied to a second counter. The first and second counters are reset and a timeout value of the second counter is identified. A first counter count value is compared with precalculated constant values. A set of range bits are latched responsive to said compared values. Two consecutive sets of latched range bits are compared and the steps repeated until a match of two consecutive sets of latched range bits is identified. The matching latched range bits are applied to a programmable range select input of the phase locked loop (PLL) circuit.

REFERENCES:
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patent: 4876518 (1989-10-01), Perkins
patent: 5015970 (1991-05-01), Williams et al.
patent: 5168245 (1992-12-01), Koskowich
patent: 5311149 (1994-05-01), Wagner et al.
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patent: 5422911 (1995-06-01), Barrett, Jr. et al.
patent: 5619484 (1997-04-01), Yokota et al.

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