Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-06-22
1996-11-12
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375362, 327156, 327160, H03D 324
Patent
active
055747574
ABSTRACT:
A phase-locked loop circuit comprises a plurality of memory counters which generate respective timing clocks corresponding to phase components detected from an input clock signal at different time instants having a predetermined time interval. Of the timing clocks, a single timing clock is selected such that the timing clock selected corresponds to a phase component previous to the latest phase component of the input clock signal. When the input clock signal stops dead or a substantial departure of frequency or phase occurs therein, the timing clock selected is applied as a reference clock to a phase comparator of the PLL circuit instead of the input clock signal.
REFERENCES:
patent: 4715050 (1987-12-01), Tanaka et al.
patent: 5034967 (1991-07-01), Cox et al.
patent: 5095498 (1992-03-01), DeLuca et al.
Chin Stephen
NEC Corporation
Nguyen Thuy L.
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