Phase-locked loop circuit having a lock state detecting function

Details Phase-locked loop circuit having a lock state detecting function Phase-locked loop circuit having a lock state detecting function

1997-08-22

1999-11-02

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 17, 331 25, H04L 706

Patent

active

059784270

ABSTRACT:
A PLL circuit detects a locked state as keeping always constant the ratio of an input signal to a locked state detection reference value by automatically and continuously changing the locked state detection reference value even when the frequency of the input signal is changed. A division ratio of a frequency divider in the PLL circuit is changed in response to an external signal. An analog signal Vc which is output from a loop filter 3 is applied to a delay circuit 7. When the analog signal Vc rises, a delay time Td of the delay circuit 7 decreases. The locked state detection reference value varies according to the frequency of the signal f1.

REFERENCES:
patent: 4494021 (1985-01-01), Bell et al.
patent: 4513427 (1985-04-01), Borriello et al.
patent: 5043677 (1991-08-01), Tomassetti et al.
patent: 5050194 (1991-09-01), Pickering et al.

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