Phase locked loop circuit for reducing electromagnetic...

Details Phase locked loop circuit for reducing electromagnetic... Phase locked loop circuit for reducing electromagnetic...

2005-05-03

2005-05-03

Callahan, Timothy P. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S074000, C327S145000, C327S147000

Reexamination Certificate

active

06888412

ABSTRACT:
For a phase-locked loop, disclosed is a method (and corresponding apparatus) for reducing electromagnetic interference caused by a clock signal produced by a voltage controlled oscillator, the method comprising: generating a control signal having a first type, e.g., sinusoidal, of slight variation in magnitude relative to a nominal magnitude value thereof; and providing the slightly varying control signal to a voltage-controlled oscillator (“VCO”) to obtain a clock signal exhibiting a second type, e.g., sinusoidal, of slight variation in frequency relative to a nominal frequency value thereof. The slight variation is non-negligible.

REFERENCES:
patent: 4963839 (1990-10-01), Stacey
patent: 5731743 (1998-03-01), Sauer
patent: 5877641 (1999-03-01), Ziegler et al.
patent: 6114914 (2000-09-01), Mar
patent: 6177844 (2001-01-01), Sung et al.
patent: 6369661 (2002-04-01), Scott et al.

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