Phase locked loop circuit, electronic device including a...

Details Phase locked loop circuit, electronic device including a... Phase locked loop circuit, electronic device including a...

2008-06-24

2008-06-24

Banks-Harold, Marsha D. (Department: 2621)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S215000, C375S294000, C375S327000, C375S331000, C375S373000, C331S135000, C331S136000, C455S258000, C455S259000, C455S260000

Reexamination Certificate

active

07391840

ABSTRACT:
A phase locked loop (PLL) circuit (1) comprising a loop input (11); a phase detector section (2) for detecting a phase difference between an input signal and a reference signal. The phase detector section (2) has a detector input connected to the loop input, a reference input and a detector output for outputting a signal related to the phase difference. A controlled oscillator (4) is connected with an input to the detector output and an oscillator output is connected to a loop output (12). The PLL has a feedback circuit which connects the oscillator output to the reference input, wherein the feedback circuit includes a device (7;71-74) having a transfer function with at least one zero.

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patent: 2003/0058055 (2003-03-01), Sridharan
patent: WO 9531861 (1995-11-01), None
Beards R D. et al., “An Oversampling Delta-Sigma Frequency Discriminator” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, IEEE Inc., New York, US, vol. 41, No. 1, 1994, pp. 26-32, XP000439300 ISSN: 1057-7130.

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