Phase locked loop circuit and method of frequency modulation...

Details Phase locked loop circuit and method of frequency modulation... Phase locked loop circuit and method of frequency modulation...

2005-08-09

2005-08-09

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

06928129

ABSTRACT:
The present invention provides a phase locked loop circuit comprising: a frequency divider for frequency-diving an output signal to generate frequency-divided pulses; an oscillator for generating the output signal under control to an oscillation frequency by a control voltage obtained from a signal corresponding to a phase difference between the frequency-divided pulses and a reference frequency signal; and a controller for performing such a control that plural kinds of frequency dividing rate are switched to be given to the frequency divider for every time period having a predetermined number of the frequency divided pulses, and at a boundary of switching the plural kinds of frequency dividing rate, the plural kinds of frequency dividing rate are given co-existentially to the frequency divider, and further for switching the coexistent plural kinds of the frequency-dividing rate, the next frequency dividing rate is given before a first appearance of a frequency peak in a transitional characteristic of the frequency of the clock signal outputted from the phase locked loop circuit caused by previous setting the frequency-dividing rate.

REFERENCES:
patent: 5257294 (1993-10-01), Pinto et al.
patent: 5604773 (1997-02-01), Urala
patent: 6049254 (2000-04-01), Knapp et al.
patent: 6225840 (2001-05-01), Ishimi
patent: 6404249 (2002-06-01), Hayashida
patent: 6496556 (2002-12-01), Huehne et al.

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