Phase locked loop circuit

Details Phase locked loop circuit Phase locked loop circuit

2001-03-27

2004-11-30

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S375000, C327S146000, C327S148000, C327S156000, C327S157000

Reexamination Certificate

active

06826248

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority right under 35 U.S.C. 119 of Japanese Patent Application No. 2000-86171 filed on Mar. 27, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit for performing a feedback control in such a manner that a phase difference and a frequency difference between a frequency divided signal generated by dividing a frequency of an oscillation signal and a reference signal becomes zero.
2. Related Background Art
FIG. 1
is a block diagram showing a schematic diagram of a conventional phase locked loop (PLL) circuit. As shown in
FIG. 1
, the conventional PLL circuit includes a phase frequency comparator
1
for outputting UP and DOWN signals in accordance with a phase difference and frequency difference between a reference signal CK
1
and a frequency divided signal CK
2
generated by dividing a frequency of an oscillation signal, a charge pump
2
whose current value changes in accordance with the UP and DOWN signals, a loop filter
3
constituted of a resistance element R
1
and capacitor elements C
1
, C
2
, a voltage control oscillator
4
for outputting an oscillation signal of a frequency corresponding to an output voltage of the loop filter
3
, and a frequency divider
5
for dividing into 1/M times the frequency of the oscillation signal to generate the frequency divided signal CK
2
.
In the PLL circuit of
FIG. 1
, when the frequency and the phase of the frequency divided signal CK
2
are behind those of the reference signal CK
1
, a current flows to the loop filter
3
from the charge pump
2
and control is performed to raise an input voltage of the voltage control oscillator
4
. Conversely, when the frequency and the phase of the frequency divided signal CK
2
are ahead of those of the reference signal CK
1
, the current flows to the charge pump
2
from the loop filter
3
and control is performed to lower the input voltage of the voltage control oscillator
4
. By such control, the frequency and the phase of the frequency divided signal CK
2
are controlled to meet those of the reference signal CK
1
.
A time required for allowing the frequency and the phase of the frequency divided signal CK
2
to meet those of the reference signal CK
1
is called lock-in time. A shorter lock-in time is more preferable. To shorten the lock-in time, it is only necessary to increase a value of the current flowing through the charge pump
2
, or to reduce capacitance of the capacities C
1
, C
2
of the loop filter
3
.
However, simply when the value of the current flowing through the charge pump
2
is increased, or the capacitance of the capacities C
1
, C
2
of the loop filter
3
a reduced, jitter increases, and an oscillation operation disadvantageously becomes unstable. That is, a stable operation of the PLL circuit and reduction of the lock-in time are originally contradictory to each other, and it is difficult to satisfy both conditions.
Furthermore, PLL circuit characteristics such as the lock-in time and jitter characteristics possibly fluctuate because of manufacturing dispersions of components constituting the PLL circuit, temperature or voltage fluctuation. Additionally, there is possibility that a system for utilizing the oscillation signal generated in the PLL circuit malfunctions.
SUMMARY OF THE INVENTION
The present invention has been developed in consideration of this respect, and an object thereof is to provide a phase locked loop circuit which can shorten a lock-in time and stabilize an oscillating operation.
To achieve the aforementioned object, there is provided a phase locked loop circuit comprising:
a phase frequency comparator configured to output an up/down signal indicating a phase difference and a frequency difference between a reference signal and a frequency divided signal;
a charge pump configured to output a current signal in accordance with said up/down signal;
oscillator configured to output an oscillation signal of a frequency in accordance with said current signal;
frequency dividing parts configured to divide the frequency of said oscillation signal and generating said frequency divided signal;
phase frequency judging parts configured to judge whether or not the phase difference and the frequency difference between said reference signal and said frequency divided signal exceed a predetermined reference value; and
changeover parts configured to switch a value of a current flowing through said charge pump depending upon whether or not the phase difference and the frequency difference between said reference signal and said frequency divided signal exceed said reference value.
According to the present invention, the current value of the current signal for controlling the oscillator is changed based on the phase and frequency differences between the reference signal and the frequency divided signal. Therefore, when the phase and frequency differences are large, the current value of the current signal is increased, and the lock-in time is shortened. When the phase and frequency differences are small, the current value of the current signal is reduced and the oscillating operation can be stabilized.
Moreover, according to the present invention, there is provided a phase locked loop circuit comprising:
a phase frequency comparator configured to output an up/down signal indicating a phase difference and a frequency difference between a reference signal and a frequency divided signal;
a charge pump configured to output a current signal in accordance with said up/down signal;
loop filter, configured to remove a high frequency component included in said current signal, said loop filter having a resistance element;
oscillator configured to output an oscillation signal of a frequency in accordance with an output voltage of said loop filter;
frequency dividing parts configured to divide the frequency of said oscillation signal to generate said frequency divided signal;
voltage detector configured to detect a voltage at both ends of said resistance element in said loop filter; and
current adjusting parts configured to adjust a value of a current flowing through said charge pump based on the detected voltage.
In the present invention, response characteristics of a phase locked loop are identified based on a result of the detected voltage at both ends of the resistance element in the filter, and the charge pump current is variably controlled in order to constantly optimize the response characteristics of the phase locked loop. Therefore, the phase locked loop circuit constantly indicates optimum response characteristics independently of manufacturing deviations, power voltage, and temperature fluctuation.


REFERENCES:
patent: 5276408 (1994-01-01), Norimatsu
patent: 5781048 (1998-07-01), Nakao et al.
patent: 6121844 (2000-09-01), Suzuki
patent: 6172571 (2001-01-01), Moyal et al.
patent: 6320435 (2001-11-01), Tanimoto
patent: 6411144 (2002-06-01), Matsuno
patent: 2001/0045849 (2001-11-01), Kurita
patent: 6-343040 (1994-12-01), None

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