Phase locked loop circuit

Details Phase locked loop circuit Phase locked loop circuit

1993-09-01

1995-04-25

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 14, H03D 324

Patent

active

054105722

ABSTRACT:
In a disclosed PLL circuit, a constant voltage output by a constant voltage power supply 6 for obtaining a signal with a frequency equivalent to that obtained in a synchronized state is added to a signal output by a filter 3 by means of an adder 7. A signal output by the adder 7 representing the sum of the voltage output by the constant-voltage power supply and the signal output by the filter is supplied to a voltage-controlled oscillator 4. With a reference signal Pi supplied, the PLL circuit functions like an ordinary PLL circuit. When the signal Pi becomes unavailable, however, a signal output by a reference-signal-input detecting circuit 5 for monitoring the reference signal Pi puts integrating components employed by the filter 3 in a short-circuit state, initializing information accumulated in the integrating components. In addition, the output of the filter is set to zero. In this state, only the constant voltage output by the constant-voltage power supply 6 is therefore supplied to the voltage-controlled oscillator 4.

REFERENCES:
patent: 4031483 (1977-06-01), Formeister
patent: 4617679 (1986-10-01), Brooks
patent: 4635280 (1987-01-01), Smith et al.
patent: 4918404 (1990-04-01), Vitiello et al.
patent: 5055801 (1991-10-01), Koga et al.
patent: 5202906 (1993-04-01), Saito et al.
"Official Action of the German Patent Office"; Aug. 16, 1994.
"Precise Simulation Model of Pulse-Phase Control Circuit for Bulk Power HVDC Transmission System", IEEE paper magazin vol. 106, No. 4, pp. 55-62 by Iwao Matori, Junichi Arai Yasuji Skine, Masahiro Ishikawa, Tsukushi Hara, Yutaka Kokai.

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