Phase locked loop capable of synchronizing output clock signal w

Details Phase locked loop capable of synchronizing output clock signal w Phase locked loop capable of synchronizing output clock signal w

1997-10-17

2000-08-15

Vo, Don N.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327157, H03D 324

Patent

active

061047716

ABSTRACT:
A phase locked loop has a voltage comparator (41) which compares a control voltage Vf supplied from a filter (15) to a voltage controlled oscillator (16) with a reference voltage VR1 supplied with a reference voltage supplying terminal (42). The reference voltage VR1 is not lower than a maximum voltage of an insensitive range of a VCO controller (17). When the control voltage Vf is lower than the reference voltage VR1, the voltage comparator 41 produces a logic high level signal. A charge pump (43) annuls a discharge signal supplied from a phase comparator (13) in response to the logic high level signal sent from the voltage comparator (41). The phase comparator (13) compares an input signal with an output clock signal supplied from the voltage controlled oscillator (16) to produce the discharge signal.

REFERENCES:
patent: 5475326 (1995-12-01), Masuda
I.A. Young, et al., "A PLL Clock Generator With 5 to 110MHz Lock Range for Microprocessors", 1992 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 50-51.

Affiliated with

Also associated with

Rating

Phase locked loop capable of synchronizing output clock signal w does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase locked loop capable of synchronizing output clock signal w, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase locked loop capable of synchronizing output clock signal w will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2015512