Phase locked loop based on a charge pump

Details Phase locked loop based on a charge pump Phase locked loop based on a charge pump

1999-12-21

2001-01-30

Vo, Don N. (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000, C327S157000

Reexamination Certificate

active

06181756

ABSTRACT:

The present invention relates to a method for balancing the output current of a charge pump according to the appended claim
1
. Also, the invention relates to a charge pump structure according to the appended claim
5
. Furthermore, the invention relates to a wireless communication device according to the appended claim
10
.
Particularly in wireless communication devices, phase-locked loops (PLL) are used as oscillators in frequency synthesis, and in the generation of clock signals. Phase-locked loops are generally implemented as integrated circuits, and the charge-pump technique is used in them. Appended
FIG. 1
shows a phase-locked loop according to prior art, comprising a phase detector PD, a charge pump CHP with two current sources CS
1
, CS
2
(FIG.
2
), a loop filter LF which is typically implemented as a low pass filter, and a voltage-controlled oscillator VCO.
FIG. 2
shows a charge pump CHP according to prior art. The phase detector PD receives two clock signals: a reference signal and a clock signal generated by the voltage-controlled oscillator. The phase detector PD comprises two output lines: UP and DOWN, the first output line DOWN being used for controlling the charging current source CS
1
of the charge pump CHP, and the second output line UP being used for controlling the discharging current source CS
2
. In a situation in which the frequency of the reference signal is greater than the frequency of the clock signal generated by the voltage-controlled oscillator VCO, or the phase of the reference signal leads the signal generated by the voltage-controlled oscillator VCO, the phase detector generates a pulse in the UP line, wherein a second switch SW
2
in the charge pump is turned off. Thus, the charging current source CS
1
is allowed to supply current to the output of the charge pump. This current i
source
from the charging current source CS
1
is supplied to the loop filter LF to increase the charge of a capacitor therein. This increase in the charge of the capacitor causes an increase in the voltage at the input of the voltage-controlled oscillator VCO. Consequently, the frequency of the clock signal generated by the voltage-controlled oscillator is increased. Correspondingly, in a situation where the frequency of the reference signal is smaller than the frequency of the clock signal generated by the voltage-controlled oscillator VCO, or the phase of the reference signal lags the signal generated by the voltage-controlled oscillator VCO, the phase detector generates a pulse in its first output, i.e. the output line DOWN, wherein a first switch SW
1
in the charge pump is turned off. Thus, the discharging current source CS
2
is allowed to drain current from the output of the charge pump, wherein the charge of the capacitor of the loop filter is discharged by the current i
sink
of this discharging current source. This reduction in the current is manifested as a reduction in the voltage at the input of the voltage-controlled oscillator. Thus, the frequency of the clock signal generated by the voltage-controlled oscillator VCO is reduced.
The above description applies to a charge pump structure in which the switches SW
1
, SW
2
are normally closed. It is also possible for the switches SW
1
, SW
2
to be in a normally open condition. In that case the operation of the switches SW
1
, SW
2
is slightly different. The UP line being used for controlling switch SW
1
and the DOWN line being used for controlling switch SW
2
. In a situation in which the frequency of the reference signal is greater than the frequency of the clock signal generated by the voltage-controlled oscillator VCO, or the phase of the reference signal leads the signal generated by the voltage-controlled oscillator VCO, the phase detector generates a pulse in the UP line, wherein a first switch SW
1
in the charge pump is turned on and the second switch SW
2
remains open. Correspondingly, in a situation where the frequency of the reference signal is smaller than the frequency of the clock signal generated by the voltage-controlled oscillator VCO, or the phase of the reference signal lags the signal generated by the voltage-controlled oscillator VCO, the phase detector generates a pulse in its first output, i.e. the output line DOWN, wherein a second switch SW
2
in the charge pump is turned on and the first switch SW
1
remains open.
It is also possible to operate the voltage-controlled oscillator VCO to operate in the opposite way—i.e. a decrease in voltage produces an increase in frequency and vice versa.
In a situation in which the reference signal and the signal generated by the voltage-controlled oscillator have the same frequency and the same phase, i.e. the phase-locked loop is in locked condition, there is no pulse in the phase detector outputs UP and DOWN. Thus, the current sources CS
1
, CS
2
of the charge pump are either switched off or both current sources CS
1
, CS
2
of the charge pump are connected to the output of the charge pump. Ideally charging current i
source
and discharging current i
sink
are designed to be the same. In an ideal situation, there should thus be no current in the output of the charge pump, and the charge of the capacitor of the loop filter should remain constant and also the frequency of the clock signal generated by the voltage-controlled oscillator VCO should remain substantially constant. In practical applications, however, the structures of the current sources CS
1
, CS
2
of the charge pump cannot be made fully identical, e.g. for the reason that the charging current source CS
1
is implemented by using a transistor of the P type or a P channel transistor, and the discharging current source CS
2
is implemented with a transistor of the N type or an N channel transistor, which cannot be made identical in practice. This results in a current mismatch of typically in the order of 5 to 20% in the currents i
source
, i
sink
of the current sources. As an example of such a known phase-locked loop, the integrated circuit LMX2335 by National Semiconductor company can be mentioned, in which the structures of the current sources are aimed at being made as identical as possible. However, also in this circuit, the current mismatch is of the order presented above.
In a situation where the phase-locked loop is in the locked condition and both current sources CS
1
, CS
2
are connected to the output of the charge pump CHP, the current mismatch leads to the capacitor of the loop filter LF being discharged or charged, depending on which current source CS
1
, CS
2
generates a current with a greater absolute value. This results in a change in the frequency of the clock signal generated by the voltage-controlled oscillator VCO. This change causes a need for correcting the phase-locked loop PLL. Thus, the frequency generated by the phase-locked loop is not constant, but it has slight variations which are manifested as an interfering signal on the other stages of the wireless communication device.
The difference in the currents i
source
, i
sink
generated by the current sources CS
1
and CS
2
is also manifested in that the frequency of the clock signal generated by the voltage-controlled oscillator VCO increases faster, if the current i
source
supplied by the charging current source CS
1
is greater, or decreases faster, if the current i
sink
drained by the discharging current source CS
2
is greater. As a result, the length of the pulses in the outputs UP and DOWN of the phase detector are not the same. This, in turn, causes interfering frequencies in the output of the phase-locked loop PLL and other spurious signals. One possibility to reduce this interference is to reduce the bandwidth of the loop filter, but this will slow down the operation of the phase-locked loop. Particularly in the next generation mobile communication systems, which are currently under development, such as the general packet radio service (GPRS), high requirements are set for the rate of frequency synthesis in the receiving and transmitting channel, because of an increasing need for ch

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