Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1997-06-16
2002-04-16
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S147000, C327S156000
Reexamination Certificate
active
06373912
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to digital control and communication arrangements. More particularly, the present invention relates to digital control arrangements used in connection with communication systems having phase-locked loop circuits.
BACKGROUND OF THE INVENTION
Phase-locked loops have become an important part of many communication systems. Phase-locked loops, sometimes referred to as PLLs, are used to synchronize signals used in the communication so that information is not lost. One basic phase-locked loop consists of a signal frequency divider, a phase detector, a low-pass filter, and a voltage-controlled oscillator. The voltage-controlled oscillator, or VCO, generates an output frequency signal that is synchronized to the input signal when the circuit is phase-locked.
Operation of such a conventional phase-locked loop, when the frequency generated by the voltage-controlled oscillator is near at multiple of the incoming frequency, is as follows. The incoming signal is compared with the feedback from the output of the voltage-controlled oscillator. The phase detector detects a phase difference, generally as a voltage whose magnitude and sign are proportional to the phase difference. This voltage is used to control the voltage-controlled oscillator in such a way that the phase-locked loop attempts to keep the phase difference between the output signal and the incoming signal as close to zero as possible.
There are many variations to the above approach and implementation details often depend on the particular application or communication system specifications. For example, a technique commonly found in frequency synthesizers is to use a divide-by-n circuit following the voltage-controlled oscillator in the feedback signal path. This circuit provides a VCO frequency that is exactly “n” times the input frequency. The variable “n” is programmed so that the phase-locked loop adjusts to synchronize a selected one of a number different possible input signals.
Another variation is to use a divide-by-n circuit following the voltage-controlled oscillator in the feedback signal path to the phase detector and a divide-by-m circuit in the path from the input signal to the other phase detector input.
A problem common to each of the above phase-locked loops is the need for the loop to minimize the phase difference quickly from start-up. For example, a slow lock-in process can cause significant interference and lack of intelligibility in both directions of communication. For battery-saving applications, such as cordless telephones, a slow lock-in process is also undesirable because the control circuitry for the cordless unit needs to shut down power from time to time to lessen the battery drain. When power to the phase-locked look resumes after power shutdown, it is important that the synchronization be reestablished as soon as possible. For such applications, a phase-locked loop with fast lock-in from start-up permits more frequent power shutdowns for increased battery savings.
SUMMARY OF THE INVENTION
One embodiment of the present invention is directed to an arrangement for phase-locking to an incoming signal. The arrangement includes a first divider circuit, a frequency-controllable oscillator, a second divider circuit and a phase detection circuit. The first divider circuit responds to the incoming signal and provides a reference signal by dividing by m during a phase-lock initiation stage and by dividing by n thereafter. The frequency-controllable oscillator provides an output signal having a frequency that is synchronized to the incoming signal when the arrangement is phase-locked to the incoming signal. The second divider circuit responds to the output signal and provides a feedback signal by dividing by x during a phase-lock initiation stage and by dividing by y thereafter. The phase detection circuit responds to the first and second divider circuits and controls the frequency-controllable oscillator so that the frequency of the output signal is synchronized to the incoming signal. In a more specific embodiment, each of the first and second divider circuits includes a switch for selecting the divide-by provision, with the switch being arranged to select the provision as a function of the phase detection circuit.
Another aspect of the present invention is directed to a method for phase-locking to an incoming signal. The method comprises dividing the incoming signal to provide a reference signal by dividing by m during a phase-lock initiation stage and by dividing by n thereafter, providing an output signal having a frequency that is synchronized to the incoming signal when the arrangement is phase-locked to the incoming signal, providing a feedback signal by dividing the output signal by x during a phase-lock initiation stage and by y thereafter, and detecting a phase difference between the feedback and reference signals and controlling the frequency-controllable oscillator so that the frequency of the output signal is synchronized to the incoming signal.
In yet another specific embodiment, the present invention is directed to phase-locking to an incoming signal involving first and second counter/switch arrangements. The first such arrangement is responsive to the incoming signal and provides a reference signal by dividing by m during a phase-lock initiation stage and by dividing by n thereafter. A voltage-controlled oscillator provides an output signal having a frequency that is synchronized to the incoming signal when the arrangement is phase-locked to the incoming signal. The second of the two counter/switch arrangements is responsive to the output signal and provides a feedback signal by dividing by x during a phase-lock initiation stage and by dividing by y thereafter. A phase detector receives the feedback and reference signals and detects a phase difference therebetween. The voltage controlled oscillator is responsive to the phase detector. A counter, responsive to the phase detector, terminates the phase-lock initiation stage by commanding the first switch to select the divide by n and the second switch to select the divide by y.
Other aspects of the present invention are directed to variations of the above embodiments.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. This is the purpose of the figures and of the detailed description that follows.
REFERENCES:
patent: 4225828 (1980-09-01), Watanabe et al.
patent: 5079520 (1992-01-01), Rapeli
patent: 5113152 (1992-05-01), Norimatsu
patent: 5220684 (1993-06-01), Suizu
patent: 5334952 (1994-08-01), Maddy et al.
patent: 5610955 (1997-03-01), Bland
patent: 5635875 (1997-06-01), Kusakabe
patent: 5774511 (1998-06-01), Boerstler
patent: 5783972 (1998-07-01), Nishikawa
Legerity Inc.
Pham Chi
Tran Khai
Williams Morgan & Amerson
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