Phase locked loop

Details Phase locked loop Phase locked loop

1999-07-21

2002-12-17

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C327S156000

Reexamination Certificate

active

06496555

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a phase locked loop, and in particular, to a phase locked loop having the capability of high speed operation.
DESCRIPTION OF THE PRIOR ART
Clock recovery circuits employing PLLs (Phase Locked Loops) have become very important in the field of data communication especially for miniaturizing devices, and a variety of PLLs have been proposed and reported. Among such techniques concerning PLLs, a PLL which is provided with a frequency comparator so as to enlarge the pull-in range (pull-in frequency range) has been disclosed in a paper: “A PLL-Based 2.5-Gb/s GaAs Clock and Data Regenerator IC”, IEEE Journal of Solid-State Circuit, vol.26, No.10, pages 1345-1353 (October 1991).
FIG. 1
is a circuit diagram showing a conventional PLL which is disclosed in the above document. The PLL shown in
FIG. 1
comprises a D-FF
70
, a delay circuit
71
, an EXOR circuit
72
, a first phase comparator
73
, a second phase comparator
74
, a VCO (Voltage Controlled Oscillator)
75
, a differential circuit
76
, a lowpass filter
77
and a mixer
78
.
An input signal is delayed by the delay circuit
71
by half the clock cycle, and the delayed input signal is supplied to the EXOR circuit
72
. Meanwhile, the input signal is also supplied to the EXOR circuit
72
directly. Thereby a pulse signal is generated by the EXOR circuit
72
when data change occurs in the input signal. The pulse signal is supplied to the first phase comparator
73
and the second phase comparator
74
, which compare the phase of the pulse signal with the phase of a clock signal which is generated by the VCO
75
. For the comparison, the clock signal having a phase 0° is supplied to the first phase comparator
73
, and the clock signal having a phase 90° is supplied to the second phase comparator
74
. The output of the first phase comparator
73
is inputted to the differential circuit
76
, and thereby a differentiated signal is supplied to the mixer
78
. Meanwhile, the output of the second phase comparator
74
is directly inputted to the mixer
78
. The mixer
78
multiplies the differentiated signal supplied from the differential circuit
76
and the output of the second phase comparator
74
together. The output of the mixer
78
is returned to the VCO
75
via the lowpass filter
77
.
The output of the lowpass filter
77
becomes a DC voltage which is proportional to the frequency difference between the input signal and the clock signal. Therefore, a PLL provided with a frequency comparator is formed by the circuit of FIG.
1
and thereby a PLL having a wide pull-in range is realized.
If we describe the clock signal having the phase 0° and the clock signal having the phase 90° as A sin ((&ohgr;t) and A cos ((&ohgr;t) respectively, the output of the first phase comparator
73
can be described as:
B
sin(
d&ohgr;t+d
&thgr;)  (1)
and the output of the second phase comparator
74
can be described as:
B
cos(
d&ohgr;t+d
&thgr;)  (2)
where d&ohgr; is the frequency difference (angular velocity difference) between the input signal and the clock signal, and d&thgr; is the phase difference between the input signal and the clock signal.
Since the output of the first phase comparator
73
is inputted to the differential circuit
76
, the output of the differential circuit
76
becomes:
d&ohgr;B
cos(
d&ohgr;t+d
&thgr;)  (3).
The signals of the expressions (2) and (3) are multiplied together by the mixer
78
, therefore, the output of the mixer
78
becomes:
d&ohgr;B
2
/2×(1+cos(2(
d&ohgr;t+d
&thgr;)))  (4).
The signal (
4
) can be divided into a DC component which is proportional to the frequency difference and an AC component whose frequency is twice the frequency difference between the input signal and the clock signal. Therefore, by removing the AC component by the lowpass filter
77
, a VCO control voltage which is proportional to the frequency difference can be obtained. By the capability of detecting the frequency difference, a PLL which is capable of enlarging the pull-in range up to the capture range of the VCO regardless of the time constant of the lowpass filter
77
and capable of operating stably is realized.
However, the conventional PLL described above requires precision of each block or component of the PLL since the frequency difference between the clock signal and the input data signal is detected in an analog manner. For example, in cases where the precision of the differential circuit
76
is deteriorated for some reason and the 90° phase shift is not executed by the differential circuit
76
precisely, an offset voltage occurs in the output of the mixer
78
. For the offset voltage, an offset compensation has to be done from outside the PLL. Further, such a high precision circuit becomes more and more harder to manufacture as the operating frequency of the PLL becomes high, and thus stable operation of the PLL in higher frequency becomes very difficult. Therefore, a PLL having wide pull-in range and capability of high speed operation is being required today.
Further, even if the pull-in could be done against the input data signal, phase difference tends to occur between the clock signal generated by the VCO and the input data signal as the bit rate of the input data signal becomes higher. In a clock recovery circuit employing a decision circuit for executing data recognition/regeneration and outputting the recognized/regenerated data, such phase difference between the clock signal and the input data signal supplied to the decision circuit has to be eliminated, that is, phase adjustment has to be executed to the clock signal which is inputted to the decision circuit so that edges (rising edges or falling edges) of the clock signal to be used for the data recognition/regeneration by the decision circuit will come to the optimum decision point (i.e. the midpoint of each time slot of the input data signal).
Such phase adjustment used to be executed by inserting a delay circuit etc. in front of the decision circuit. However, techniques for eliminating the need of the phase adjustment have been proposed these days. Such an example of a PLL has been disclosed in a paper: “A Self Correcting Clock Recovery Circuit”, IEEE Journal of Lightwave Technology, vol.LT-3, No. 6, pages 1312-1314 (December 1983).
FIG. 2
is a circuit diagram showing the conventional PLL (clock recovery circuit) which is disclosed in the above document. The PLL of
FIG. 2
is composed of a phase comparator
80
, a filter
81
and a VCO
82
. In the phase comparator
80
, a first D-FF
83
and a second D-FF
84
are connected in series. The input data signal is supplied to the data input terminal D of the first D-FF
83
. The output terminal Q of the first D-FF
83
is connected to the data input terminal D of the second D-FF
84
, and thereby recognized/regenerated input data is outputted from the output terminal Q of the second D-FF
84
. The clock terminal C of the first D-FF
83
is supplied with the clock signal from the VCO
82
, and the clock terminal C of the second D-FF
84
is supplied with an inverted clock signal which is generated by inverting the clock signal from the VCO
82
by an inverter
85
. The data input terminal D and the output terminal Q of the first D-FF
83
are connected to a first EXOR circuit
86
, and the data input terminal D and the output terminal Q of the second D-FF
84
are connected to a second EXOR circuit
87
. The outputs of the first and the second EXOR circuits
86
and
87
are supplied to an adder
88
, in which the output of the first EXOR circuit
86
is inputted to the adder
88
so as to be added and the output of the second EXOR circuit
87
is inputted to the adder
88
so as to be subtracted. The output of the adder
88
is supplied to the filter
81
, and the output of the filter
81
is returned to the VCO
82
as a control signal.
The PLL of
FIG. 2
operates as follows.
FIGS. 3 and 4
are timing charts showing the operation of the phase comparator
80
of the

Affiliated with

Also associated with

Rating

Phase locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase locked loop will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2966668