Phase locked loop

Details Phase locked loop Phase locked loop

2011-01-04

2011-01-04

Pathak, Sudhanshu C (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C375S327000, C327S156000, C341S155000, C331S017000, C331S078000, C331S100000

Reexamination Certificate

active

07864910

ABSTRACT:
A PLL is provided with an optimum operating point in order to have appropriately a frequency margin and a locking time. There is provided a phase looked loop which includes: a frequency divider for dividing an output signal by a dividing integer corresponding to an input code; an encoding unit for encoding the input code to generate an encoded code; and a loop filtering unit configured to adjust elements in response to the encoded code.

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