Phase-locked loop

Details Phase-locked loop Phase-locked loop

1997-03-20

1998-10-06

Dinh, Son T.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 1A, 327147, 327148, H03B 524, H03L 706

Patent

active

058183043

ABSTRACT:
A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO), a charge pump, a phase detector and a frequency detector. The phase detector detects the phase difference between an incoming signal and a VCO signal. The frequency difference between the incoming signal and a reference signal is detected by the frequency detector separately from the phase detector. During the process of attaining phase lock, the phase and frequency detectors operate simultaneously. The VCO signal is phase-locked to the incoming signal when it is present. When the incoming signal is absent, the VCO maintains a frequency close to an intended bit rate by frequency locking to a multiple of the reference signal. It, thus, avoids extreme system behavior and greatly assists rapid reliable phase lock when the incoming signal is applied following a period when it is absent. The PLL is analog for simplicity, low power, and the ability to achieve the finest possible phase resolution, while the frequency lock mode is digitally controlled for high parametric insensitivity and ease of disabling to minimize power consumption and jitter once phase lock is attained. The frequency detector includes two counters for counting the VCO and reference signals. The frequency detector inhibits either of the counters as needed to force them both to count at the same rate and uses inhibit pulses to control a separate charge pump connected directly to the integration capacitor of the PLL. The frequency detector can be easily added to a wide range of charge pump PLLs.

REFERENCES:
patent: 5072195 (1991-12-01), Graham et al.
patent: 5334951 (1994-08-01), Hogeboom
patent: 5491439 (1996-02-01), Kelkar et al.
patent: 5566204 (1996-10-01), Kardontchik et al.
patent: 5610560 (1997-03-01), Sauer et al.
patent: 5646968 (1997-07-01), Kovacs et al.
"Charge-Pump Phase-Lock Loops", F.M. Gardner, IEEE Transactions on Communications, vol. COM-28, No. 11, Nov. 1980, pp. 1849-1858.
"Design of PLL-Based Clock Generation Circuits", D-K Jeong et al, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.
"A PLL Clock Generator with 5 to 110 Mhz of Lock Range for Microprocessors", I.A. Young et al, IEEE journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1606.

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