Phase lock loop with cycle drop and add circuitry

Details Phase lock loop with cycle drop and add circuitry Phase lock loop with cycle drop and add circuitry

2006-08-08

2006-08-08

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S148000, C327S157000

Reexamination Certificate

active

07088797

ABSTRACT:
Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

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patent: 2003/0026368 (2003-02-01), Subramoniam et al.
patent: 2004/0042474 (2004-03-01), Walker et al.

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