Phase-lock loop initialized by a calibrated oscillator-control v

Details Phase-lock loop initialized by a calibrated oscillator-control v Phase-lock loop initialized by a calibrated oscillator-control v

1994-01-21

1995-12-05

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 18, H03D 320

Patent

active

054736404

ABSTRACT:
A phase-lock loop (FIG. 1) is initialized at power-up by an oscillator (14) control signal (28) that has previously been stored by a processor (20) in a non-volatile memory (27). The stored control signal is generated by the phase-lock loop's controller (12) in response to receipt of a calibrated reference input signal, as part of manufacturing of the phase-lock loop and occasionally thereafter during normal operation. Being stored in non-volatile memory, the control signal is not lost upon removal of power from the phase-lock loop. The stored control signal is then used to control the oscillator instead of the controller's output upon power-up and until the later one of (a) receipt by the phase-lock loop of a valid reference signal and (b) receipt of a directive for the controller to take over control of the oscillator.

REFERENCES:
patent: 4516250 (1985-05-01), Grimes
patent: 4633193 (1986-12-01), Scordo
patent: 4703520 (1987-10-01), Rozanski, Jr. et al.
patent: 4930142 (1990-05-01), Whiting et al.
patent: 4972442 (1990-11-01), Steierman
patent: 4980899 (1990-12-01), Troost et al.
patent: 5028885 (1991-07-01), Voigt et al.
patent: 5041798 (1991-08-01), Moorman et al.

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