Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-09-24
2003-05-27
Tse, Young T. (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S156000, C331S011000, C331S017000
Reexamination Certificate
active
06570947
ABSTRACT:
FIELD OF THE INVENTION
A method and system for calibrating a phase lock loop having a robust bandwidth.
BACKGROUND OF THE INVENTION
Phase lock loops (i.e.—PLLs) are used in a variety of integrated circuits. Prior art PLLs are comprised of a phase detector, a loop filter, a frequency divider and either one of the following types of controlled oscillators: voltage controlled oscillator (VCO), digital controlled oscillator (DCO) or current controlled oscillator (ICO). A frequency of an output signal of a controlled oscillator is responsive to a control signal provided to the controlled oscillator. The frequency divider receives an output signal provided by a controlled oscillator having a frequency of Fvco and outputs a signal having frequency of (Fvco/N). Usually, N is proportional to Fvco, and it ranges between Nmin and Nmax, where Nmax>>Nmin.
Usually, Nmax>NminX
8
. Prior art PLL have a transfer function Hpa(s) that is characterized by having a bandwidth BWpa (N) that is dependant upon the value of N. BWpa (N) ranges from a minimum of BWmin to a maximum of BWmax, wherein BWmin>BWmax, larger values of N result in a narrower bandwidth.
On one hand, a large bandwidth allows the PLL to respond in a quick manner to eventual frequency and/or phase errors and minimize jitter. On the other hand, narrow bandwidth is required in order to achieve good rejection capability of high frequency noise. Narrow bandwidth allows to reject high frequency fluctuations in clock signals and jitter resulting from the frequency division performed by the frequency divider.
In prior art PLL it is difficult to reconcile these contrasting requirements. Usually, BWmax has to be narrow enough so that the PLL has a good rejection capability of high frequency noise and BWmin has to be large enough to allow quick response to eventual frequency and/or phase errors.
U.S. Pat. No. 5,382,922 of Gerbach et al discloses a system and method for calibrating a PLL and to provide a precise setting of the center frequency of a VCO. As seen in
FIG. 1
of U.S. Pat. No. 5,382,922, the PLL includes a phase detector, a charge pump, a loop filter, a voltage to current converter, an ICO and a calibration circuit. Although
FIG. 1
does not disclose a frequency divider, such a frequency divider is disclosed in FIG.
3
. The calibration involves adding a bias current to the input of the ICO, the bias current is calculated so that the PLL will output a central frequency at the middle of a control voltage range, the control voltage range is provided by the charge pump. The calibration circuit includes two comparetors that indicate whether the control voltage Vc is below or above two reference signals VR
1
and VR
2
, where VR
1
>VR
2
, which are usually chosen near the central frequency. The calibration process involves adjusting the bias current according to the relations between VR
1
, VR
2
and Vc. If Vc<VR
1
the bias current is lowered, if Vc>Vr
2
the current bias is increased. Usually the calibration process involves a plurality of adjustments, whereas after each adjustment the PLL has to perform a phase lock. Thus, the calibration procedure is relatively long, the calibration circuit is provided with a clock CAL_CLK having a period that is much longer than the period in which a PLL performs a frequency/phase lock. The calibration takes several CAL_CLK periods. Another disadvantage of the PLL disclosed in U.S. Pat. No. 5,382,922 is that is does not adjust itself to changes in N, thus the frequency range, and accordingly the frequency step are fixed.
Component tolerances and process variations often result in a wide range of possible controlled oscillator gain and loop filter gain that can decrease the dynamic range of the PLL. It is desirable to have a PLL that has a dynamic range that is less sensitive to these tolerances and variations.
REFERENCES:
patent: 4380742 (1983-04-01), Hart
patent: 5079521 (1992-01-01), Gaskell et al.
patent: 5105160 (1992-04-01), Summers
patent: 5111151 (1992-05-01), Ii
patent: 5168245 (1992-12-01), Koskowich
patent: 5173617 (1992-12-01), Alsup et al.
patent: 5268653 (1993-12-01), Lafon
patent: 5347234 (1994-09-01), Gersbach et al.
patent: 5349311 (1994-09-01), Mentzer
patent: 5382922 (1995-01-01), Gersbach et al.
patent: 5574455 (1996-11-01), Hori et al.
patent: 5625358 (1997-04-01), Wilson et al.
patent: 5654675 (1997-08-01), Bruccoleri et al.
patent: 5668503 (1997-09-01), Gersbach et al.
patent: 5727038 (1998-03-01), May et al.
patent: 5745533 (1998-04-01), Asada et al.
patent: 5748043 (1998-05-01), Koslov
patent: 5844447 (1998-12-01), Choi
patent: 5844954 (1998-12-01), Casasanta et al.
patent: 5856762 (1999-01-01), Werker et al.
patent: 5867333 (1999-02-01), Saiki et al.
patent: 5892406 (1999-04-01), Dicke et al.
patent: 5986485 (1999-11-01), O'Sullivan
patent: 6005425 (1999-12-01), Cho
patent: 6150887 (2000-11-01), Yamaguchi
Afek Yachin
Zarubinsky Michael
Zipper Eliav
Motorola Inc.
Tse Young T.
LandOfFree
Phase lock loop having a robust bandwidth and a calibration... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Phase lock loop having a robust bandwidth and a calibration..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase lock loop having a robust bandwidth and a calibration... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3051888