Phase lock loop circuit using a sample and hold switch circuit

Details Phase lock loop circuit using a sample and hold switch circuit Phase lock loop circuit using a sample and hold switch circuit

1994-02-14

1996-09-17

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 16, 331 1A, H03D 324

Patent

active

055576486

ABSTRACT:
A phase lock loop circuit that can be formed into a full monolithic integrated circuit without an external component part, and that can maintain the phase locked state even for a consecutive identical bit state of input data including more than several tens of consecutive identical bits. The input data applied to a data input terminal is doubled in frequency by a doubler. A phase difference between the output of the doubler and that of a VCO is detected by a phase comparator, and is supplied to a low-pass filter through a sample and hold switch circuit. The low-pass filter produces a DC output corresponding to the phase difference, and supplies it to the frequency control terminal of the VCO. The output frequency of the VCO is controlled so that the phase difference becomes zero. The sample and hold switch circuit is maintained at the off state (holding mode) during the consecutive identical bit state to hold the output of the low-pass filter, so that the VCO continues that frequency at the beginning of the consecutive identical bit state.

REFERENCES:
patent: 3573649 (1971-04-01), West
patent: 4061979 (1977-12-01), Walker et al.
patent: 4825437 (1989-04-01), Balech
patent: 5028885 (1991-07-01), Voigt et al.
patent: 5036298 (1991-07-01), Bulzachelli
Lawrence Devito et al, "TPM 8.6: A 52 Mhz and 155 MHz Clock-Recovery PLL", IEEE International Solid-State Circuits Conference, Feb. 14, 1991, pp. 142, 143 & 306.
Mihai Banu et al, "TA 6.4: A 660Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Bursi-Mode Transmission", IEEE International Solid-State Circuits Conference, Feb. 25, 1993, pp. 102 & 103.
Mehmet Soyuer et al, "TP 10.4: A Monolithic 2.3Gb/s 100m W Clock and Data Recover Circuit", IEEE International Solid-State Circuits Conference, Feb. 25, 1993, pp. 158 & 159.

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