Phase jump sequencer architecture

Details Phase jump sequencer architecture Phase jump sequencer architecture

2011-05-31

2011-05-31

Ahn, Sam K (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

07953200

ABSTRACT:
A method for controlling an output phase of a phase interpolator, by forming an M bit control word, designating N bits of the control word as a fractional number portion, designating M-N bits of the control word as a whole number portion, adjusting a phase jump of the phase interpolator at a designated clock cycle by a first number of phases as designated by the whole number portion plus a second number of phases as designated by the fractional number portion. The designated clock cycle can be identified by numbering clock cycles with a count value from counter having a repeating period of 2N, and for each clock cycle identified by a multiple of the count value of 2kwithin the repeating period, where k is a bit-wise position within the fractional number portion having a value of 0≦k≦N-1, the second number of phases can equal a binary value of the fractional number portion at the kthposition, for any k.

REFERENCES:
patent: 2006/0245531 (2006-11-01), Leonowich et al.

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