Phase interpolator for a timing signal generating circuit

Details Phase interpolator for a timing signal generating circuit Phase interpolator for a timing signal generating circuit

2009-01-23

2011-11-22

Bae, Ji H (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S400000, C713S503000, C331S00100A

Reexamination Certificate

active

08065553

ABSTRACT:
A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

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