Phase interpolator circuit with two phase capacitor charging

Details Phase interpolator circuit with two phase capacitor charging Phase interpolator circuit with two phase capacitor charging

2008-11-13

2011-11-22

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

C237S049000, C237S049000, C237S049000

Reexamination Certificate

active

08063686

ABSTRACT:
In one embodiment of the invention, a method is disclosed to generate a clock output signal with selected phase. The method includes selecting a phase delay for the clock output signal; charging a capacitor with a first weighted current during a first phase input clock, charging the capacitor with a second weighted current during a portion of a second phase input clock, and determining if a voltage across the capacitor is greater than or equal to a threshold voltage to generate a first edge of the clock output signal with the selected phase delay. The first weighted current may have a weighting of N out of M to charge the capacitor with a predetermined rate of change in voltage in response to the selected phase delay. The second weighted current may have a weighting of M out of M to charge the capacitor with a constant rate of change.

REFERENCES:
patent: 5021749 (1991-06-01), Kasai et al.
patent: 5898328 (1999-04-01), Shoji
patent: 2003/0215039 (2003-11-01), Block et al.
patent: 2006/0256911 (2006-11-01), Rosik et al.
patent: 2007/0030046 (2007-02-01), Pai et al.
patent: 2007/0273415 (2007-11-01), Kimura et al.
patent: 2009/0108892 (2009-04-01), Chen et al.

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