Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-03-03
2003-07-29
Vo, Don N. (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S156000, C331S011000
Reexamination Certificate
active
06600797
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to an optical transmission system, and particularly to a phase synchronism circuit for use in optical fiber transmission.
In the optical transmission system, a photodetector photoelectrically converts a received optical signal to an electrical signal. The NRZ coded binary data produced after this converted electrical signal is equalized, amplified and digitized has small jitter when the received optical level is large, but increases the jitter as the received optical level decreases. When no optical signal is detected, noise output is produced which corresponds to infinite jitter. In addition, a pulse width distortion is caused in this data by optical transmission and receiving circuits.
FIG. 1
shows the construction of a related phase frequency synchronism circuit that generates from such data signal a clock signal synchronized with that data. Referring to
FIG. 1
, there is shown a phase comparator
10
that generates a pulse voltage of a peak value or pulse width corresponding to the phase difference between the input data and the clock signal. A frequency comparator
20
produces the difference of the frequency of the clock signal to the transmission rate of the input data. When the input data and the clock signal are synchronized to within a predetermined phase difference, no frequency difference is produced. The output from the phase comparator
10
and the output from the frequency comparator
20
are supplied through an overlap unit
80
to a loop filter
40
. A VCO (voltage controlled oscillator, hereinafter referred to as VCO)
50
generates the clock signal with the oscillation frequency changed on the basis of the output from the loop filter
40
, and feeds it back in order that the input data and the clock signal can be synchronized with each other. The phase frequency synchronism circuit of this construction is described in, for example, “TP10.3:A 8 Gb/s Si Bipolar Phase and Frequency Detector IC for Clock Extraction”, 1992 IEEE International Solid-State Circuits Conference, p. 162, and JP-A-6-216766.
A storaging apparatus using disks has vibration of about 1% of the data rate because of irregular rotation of disks. As compared with the data signal from the optical receiver, the data signal from the filing apparatus has small jitter and pulse width distortion.
FIG. 2
shows the construction of a related phase frequency synchronism circuit that generates from the data signal a clock signal synchronized with that data. Referring to
FIG. 2
, there is shown a first phase comparator
10
-
1
that generates a pulse voltage of a pulse with corresponding to the phase difference between the input data and the clock signal. A rate (frequency) comparator
600
compares the input data and the clock signal to detect if the clock signal exceeds a specified limit of the mark length of the data, and produces the decision output of if the bit rate (frequency) of the clock is higher or lower than that of the data.
A second phase comparator
10
-
2
generates a pulse voltage of a pulse width corresponding to the leading or lagging phase difference between the input data and the clock signal. The second phase comparator
10
-
2
receives the input data, the clock signal and the output from the rate comparator
600
and generates the pulse voltage of the pulse width corresponding to either leading or lagging phase difference between the input data and the clock signal according to the output from the rate comparator
600
. A synchronous identifying unit
30
compares the input data and the clock signal to detect if the clock signal exceeds a specified limit of the mark length of the data, thus deciding if the input data and the clock signal are synchronized. A switch
1
is provided between the output of the first phase comparator
10
-
1
and a first loop filter
40
-
1
and operated to close or open when the synchronous identifying unit
30
decides that those signals are synchronized or not synchronized, respectively. A switch
2
is placed between the output of the second phase comparator
10
-
2
and a second loop filter
40
-
2
and operated to open or close when the synchronous identifying unit
30
decides that those signals are synchronized or not synchronized, respectively. The outputs from the first and second loop filters
40
-
1
,
40
-
2
are supplied through an adder
90
to the VCO
50
. The VCO
50
produces the clock signal with its oscillation frequency changed in accordance with the output from the adder
90
, and feeds it back in order that the input data and the clock signal can be synchronized. The phase frequency synchronism circuit of this construction is described in JP-A-9-284269.
In the phase frequency synchronism circuit shown in
FIG. 1
, the loop filter constant is determined by the characteristic of the loop of the phase comparator
10
, loop filter
40
and VCO
50
when the input data and the clock signal are synchronized. A loop of the frequency comparator
20
, loop filter
40
and VCO
50
is used when the input data and the clock are not synchronized. Since the loop filter constant for the asynchronous state cannot be selected, there is a problem that it takes a long time to reach the synchronous state from the asynchronous state.
Let us consider that in the phase frequency synchronism circuit shown in
FIG. 2
, the frequencies of the input data and clock signal become close to each other from the asynchronous state in which the switches
1
and
2
are respectively opened and closed, resulting in the generation of a “synchronous” deciding signal from the synchronous identifying unit
30
. The generation of the “synchronous” deciding signal means that the output from the adder
90
, or the sum of the output from the first loop filter
40
-
1
and the output from the second loop filter
40
-
2
approaches a predetermined value relative to the oscillation frequency of the VCO
50
. It is supposed from this situation that there is a voltage level difference between the output from the first phase comparator
10
-
1
and the output from the first loop filter
40
-
1
. When the switches
1
and
2
are closed and opened, respectively, there is a possibility that the output from the adder
90
suddenly changes due to the voltage level difference between the output of the first phase comparator
10
-
1
and the output of the first loop filter
40
-
1
, making the phase frequency synchronism circuit unstable. Therefore, although the phase frequency synchronism circuit of
FIG. 2
having the two loop filters is able to separately set the frequency pull-in characteristic and phase pull-in characteristic, it may become unstable when switching is made from the frequency pull-in mode to the phase pull-in mode.
In addition, let us consider that the phase frequency synchronism circuit of
FIG. 1
receives binary data with large jitter resulting from equalizing, amplifying and digitizing a faint optical signal. Even when the synchronism circuit shown in
FIG. 1
achieves that the input data and the clock signal are synchronous in their phases, the input jitter may instantaneously exceed a certain phase difference to cause the frequency comparator
10
to be operative so that the clock jitter increases in an instant. In the phase frequency synchronism circuit of
FIG. 2
, when the input jitter instantaneously exceeds a predetermined phase difference, the synchronous identifying unit
30
may decide by mistake that the input data and the clock signal are asynchronous by mistake. As a result, switching is made from the phase synchronous mode to the frequency synchronous mode so that the clock jitter increases. If a phase frequency synchronism circuit having a characteristic to increase jitter in the clock signal is used in the optical receiver, the error rate may suddenly increase.
In addition, when the input data is generally NRZ coded and has pulse width distortion, a phase comparator that generates a voltage of a peak value or pulse width corresponding to the phase difference of the clock si
Aoki Tetsuya
Hasegawa Atsushi
Yamashita Takeshi
Townsend and Townsend / and Crew LLP
Vo Don N.
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