Phase/frequency estimator-based phase locked loop

Details Phase/frequency estimator-based phase locked loop Phase/frequency estimator-based phase locked loop

2011-01-11

2011-01-11

Tse, Young T. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S156000

Reexamination Certificate

active

07869554

ABSTRACT:
A phase/frequency estimator-based phase locked loop (PFE-PLL) may be use to obtain a phase and frequency estimation by using an algebraic summer, a gain block and a (co)sine waveform generator. The apparatus and methods of the present invention may provide the phase estimation of an input signal from which a frequency of the signal is estimated by a derivative function. Unlike conventional phase lock loop systems, which may use a multiplier to perform complex calculations on an input and a feedback signal to develop a demodulated voltage output, the present invention may use a simple algebraic summer to provide an error signal and output a phase and a frequency estimation of the input signal.

REFERENCES:
patent: 4495475 (1985-01-01), Mark et al.
patent: 4771250 (1988-09-01), Statman et al.
patent: 6046645 (2000-04-01), Cucchi et al.
patent: 6137326 (2000-10-01), Ogawa
patent: 2001/0038316 (2001-11-01), Kondoh
patent: 2005/0046489 (2005-03-01), Cranford et al.

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