Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-06-26
2001-07-10
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S373000, C327S003000, C327S012000, C331S011000
Reexamination Certificate
active
06259754
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a phase-locked loop (PLL) for liquid crystal displays (LCDs) which generates a master clock signal, and more particularly to a phase frequency detection circuit and a method for detecting the phase frequency difference between an external synchronous signal and a horizontal synchronous signal from the PLL with accuracy.
In general, a conventional phase-locked loop (PLL) for generating a master clock signal MCLK for LCDs is shown in FIG.
6
. In the conventional PLL, the phase frequency detector
100
compares the phase between an external synchronous signal Csa and a horizontal synchronous signal Hs from a horizontal synchronous signal generator
500
to generate a phase frequency difference signal PFD. A voltage controlled-oscillator
400
varies its oscillation frequency with the phase frequency difference signal PFD received from the phase frequency detector
100
through a low pass filter LPF
200
and a buffer
300
to generate a master clock signal MCLK. A horizontal synchronous signal generator
500
generates the horizontal synchronous signal Hs to the phase frequency detector
100
in accordance with the master clock signal MCLK. At this time, the external synchronous signal Csa which is externally provided to the phase frequency detector
100
is a signal where video signal, equalization pulse signal and vertical synchronous signal are removed from the composite synchronous signal by using a RC constant of a multivibrator.
The prior phase frequency detector
100
used in the PLL is comprised of a three-state buffer as shown in FIG.
4
. The three-state buffer
90
of the prior phase frequency detector
100
is enabled in the low state period of the external synchronous signal Csa as shown in
FIG. 5A
to output the horizontal synchronous signal Hs as shown in
FIG. 5B
received from the horizontal synchronous signal generator
500
and is disabled in the high state period of the external synchronous signal Csa, thereby being high impedance. Accordingly, the three-state buffer
90
generates the phase frequency difference signal PFD as shown in FIG.
5
C.
However, the prior phase frequency detector
100
compares the phase between the external synchronous signal Csa and the horizontal synchronous signal Hs to generate the phase frequency difference signal PFD only when the external synchronous signal Csa is in low state. Therefore, it is impracticable to detect the phase frequency difference between the external synchronous signal Csa and the horizontal synchronous signal Hs with accuracy, unless the horizontal synchronous signal Hs is overlapped with the external synchronous signal Csa of low state. In addition, if the period of the external synchronous signal Csa is different from that of the horizontal synchronous signal Hs, the phase frequency detector
100
detects the undesired phase frequency difference signal PFD.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a phase frequency detector for LCD capable of detecting a phase frequency difference between an external synchronous signal and a horizontal synchronous signal from the PLL with accuracy.
Another object of the present invention is to provide a method for detecting a phase frequency difference between an external synchronous signal and a horizontal synchronous signal from the PLL with accuracy by dividing the external synchronous signal and the horizontal synchronous signal and comparing the divided horizontal synchronous signa and the divided external synchronous signal.
According to an aspect of the present invention, there is provided to a phase frequency detection circuit of a phase locked loop (PLL) for liquid crystal display which compares a phase between an external synchronous signal and a horizontal synchronous signal from the PLL to generate a phase frequency difference signal, comprising:
a dividing means for dividing the external synchronous signal and the horizontal synchronous signal; a phase difference detecting means for detecting the phase difference between the divided external synchronous signal and the divided horizontal synchronous signal from the dividing means; a phase discriminating means for discriminating whether the phase of the divided external synchronous signal is ahead of that of the divided horizontal synchronous signal and generating the phase discriminating signal; and a comparison means for receiving the phase difference detection signal from the phase difference detection means and the phase discriminating signal from the phase discriminating means to generate the phase frequency difference signal.
In accordance with an embodiment of the present invention, the dividing means includes:
a first dividing means for dividing the external synchronous signal by two; and a second dividing means for dividing the horizontal synchronous signal by two. The first dividing means comprises:
a first flip flop which receives its inverted output signal as its input signal and is triggered at the negative edge of the external synchronous signal and generates the 2-divided external synchronous signal as an output signal to the phase difference detection means and the phase discriminating means; and a first inverter which inverts the output signal of the first flip flop and the inverted output signal is provided to the input signal of the first filp flop. The second dividing means comprises:
a second flip flop which receives its inverted output signal as its input signal and is triggered at the negative edge of the horizontal synchronous signal and generates the 2-divided horizontal synchronous signal as an output signal to the phase difference detection means and the phase discriminating means; and a second inverter which inverts the output signal of the second flip flop and the inverted output signal is provided to the input signal of the second flip flop.
The phase difference detection means comprises an exclusive NOR gate which receives the 2-divided external synchronous signal from the first dividing means and the 2-divided horizontal synchronous signal from the second dividing means and logically operates two signals to generate the phase difference detection signal to the comparison means.
The phase discriminating means comprises:
a first detection means for receiving the 2-divided external synchronous signal from the first dividing means and a master clock signal generated from the PLL and detecting the level transition of the 2-divided external synchronous signal at the positive edge of the master clock signal; a second detection means for receiving the 2-divided horizontal synchronous signal from the second dividing means and a master clock signal generated from the PLL and detecting the level transition of the 2-divided horizontal synchronous signal at the positive edge of the master clock signal; and a generation means for receiving output signals from the first and second detection means and discriminating the phase of the 2-divided external synchronous signal and the 2-divided horizontal synchronous signal to generate the phase discriminating signal to the comparison means.
The first detection means comprises:
a first flip flop which receives the 2-divided external synchronous signal from the first dividing means and the master clock signal generated from the PLL and is triggered at the positive edge of the master clock signal to delay the 2-divided external synchronous signal; and a first exclusive OR gate for logically operating the 2-divided external synchronous signal delayed from the first flip flop and the 2-divided external synchronous signal received from the first dividing means to detect the level transition of the 2-divided external synchronous signal.
The second detection means comprises:
a second flip flop which receives the 2-divided horizontal synchronous signal from the second dividing means and the master clock signal generated from the PLL and is triggered at the positive edge of the master clock signal to delay the 2-divided horizontal synchronous signal; and a second exclusive
Chin Stephen
Ghayour Mohammad
Hyundai Electronics Industries Co,. Ltd.
Selitto Behr & Kim
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