Phase error determination method and digital phase-locked...

Details Phase error determination method and digital phase-locked... Phase error determination method and digital phase-locked...

2008-01-01

2008-01-01

Torres, Joseph D. (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data pulse evaluation/bit decision

Reexamination Certificate

active

07315968

ABSTRACT:
In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

REFERENCES:
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patent: 4466089 (1984-08-01), Wachi
patent: 4539666 (1985-09-01), Wachi
patent: 5400370 (1995-03-01), Guo
patent: 09-247137 (1997-09-01), None
patent: 11-341306 (1999-12-01), None

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