Phase error cancellation method and apparatus for high performan

Details Phase error cancellation method and apparatus for high performan Phase error cancellation method and apparatus for high performan

1997-06-27

1999-10-05

Ghebretinsae, Temesghen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

370517, 327161, H04L 700

Patent

active

059636068

ABSTRACT:
A phase error cancellation apparatus captures data bits of a serialized data stream with reduced phase error by aligning a generated clock signal to the data stream. The phase error cancellation apparatus includes a data delay pipe, a clock generator, a clock delay pipe, and a data stream sampling element. The data delay pipe receives the data stream and delays the data bits by a first amount. The clock generator generates a clock signal that the clock delay pipe delays by a second amount. The data stream sampling element receives the delayed data bits and the delayed clock signal, and samples the delayed data bits using the delayed clock signal to recover the data bits from the data stream with reduced phase error.

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