Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1998-10-27
2000-10-03
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
327153, 713401, 713500, H04L 700
Patent
active
061283592
ABSTRACT:
An apparatus and method for indicating a phase difference between a first input signal and a second input signal. A first delayed signal is generated by delaying a reference signal for a first predetermined time and a second delayed signal is generated by delaying the reference signal for a second predetermined time, the second predetermined time being longer than the first predetermined time. The leading signal of the first and second input signals is detected. If the first input signal leads the second input signal, the first delayed signal is output to represent the first input signal and a signal that lags the first delayed signal by a third predetermined time is output to represent the second input signal. If the second input signal leads the first input signal, the second delayed signal is output to represent the first input signal and a signal that leads the second delayed signal by a fourth predetermined time is output to represent the second input signal.
REFERENCES:
patent: 5073886 (1991-12-01), Sasaki et al.
patent: 5459755 (1995-10-01), Iga et al.
patent: 5945849 (1999-08-01), Yamamoto
patent: 6000022 (1999-12-01), Manning
Advanced Information, "Direct RMC.d1 Data Sheet", Rambus Inc., www.rambus.com, DL0036-00.7, Aug. 1998, pp. 1-104.
Chin Stephen
Fan Chieh M.
Intel Corporation
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