Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-06-26
2001-05-08
Tse, Young T. (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S236000, C331S014000, C331S025000
Reexamination Certificate
active
06229865
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a phase-locked loop (PLL) for liquid crystal displays (LCDs) which generates a master clock signal synchronized with an external synchronous signal, and more particularly to a phase difference detector for preventing the phase difference variation due to an equalization signal.
In general, thin film transistor-liquid crystal displays (TFT-LCDs) generate a master clock signal synchronized with an external synchronous signal through a PLL.
FIG. 1
shows a block diagram of the prior PLL circuit for generating a master clock signal in TFT-LCDs. The prior PLL circuit compares the phase between an external synchronous signal Csync and an internal synchronous signal Hsync from a synchronous signal generator
60
through a phase difference detector
10
to generate a phase difference detection signal PFD.
A voltage controlled oscillator (VCO)
30
varies its oscillation frequency according to the phase difference detection signal PFD to generate the master clock MCLK. A sampling clock signal generator
70
receives the master clock signal MCLK from the VCO
30
through a buffer
40
to generate sampling clock pulse CPH for sampling R, G and B data. Accordingly, the prior PLL circuit generates the master clock signal MCLK synchronized with the synchronous signal Csync as the VCO
30
varies the frequency of the master clock signal MCLK according to the phase difference detection signal PFD generated from the phase difference detector
10
.
However, if a composite synchronous signal is received as the external synchronous signal, the equalization period is exist in a vertical synchronous signal. Because the equalization pulse having a 1/H period is exist in the equalization period, if the phase difference detector compares the phase between two synchronous signals, the frequency of the VCO
30
is abruptly varied by the excessive phase variation. Although in the vertical synchronous signal period video signals are not displayed, it takes a long time to completely stabilize the abrupt frequency variation in the equalization period, thereby affecting the early display of video signals. Accordingly, the distortion is occurred in the upper end of a screen.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a phase detector for LCD capable of being carrying out the stable phase difference detection by masking the phase difference detection operation in the equalization period of the composite synchronous signal.
According to an aspect of the present invention, there is provided to a phase difference detection circuit of a phase locked loop (PLL) for liquid crystal display which compares a phase between an external synchronous signal and an internal synchronous signal from the PLL to generate a phase difference detection signal, comprising: a phase comparison means for comparing the phase between the external synchronous signal and the internal synchronous signal to generate the phase difference detection signal; an equalization pulse detection means for detecting an equalization pulse from the external and internal synchronous signals and generating a control signal for controlling the output of the phase difference detection signal from the phase comparison means according to an equalization pulse detection signal; an output selection means for masking the phase difference detection signal from the phase comparison means in an equalization period and providing the phase difference detection signal in a non-equalization period according to the control signal received from the equalization pulse detection means; and an equalization period ending detection means for detecting an equalization period ending to generate an equalization period ending detection signal to the equalization pulse detection means according to the control signal and the equalization pulse detection signal received from the equalization pulse detection means.
The equalization pulse detection means includes: a detection means for detecting the equalization pulse from the external synchronous signal and the internal synchronous signal and providing the equalization pulse detection signal to the equalization period ending detection means; a control signal generation means for receiving the equalization pulse detection signal received from the detection means to generate the control signal for controlling the output of the phase difference detection signal generated from the phase comparison means to the output selection means and the equalization period ending detection means; and a trigger signal generation means for receiving the equalization period ending detection signal received from the equalization period ending detection means to generate the trigger signal for triggering the control signal generation means.
The detection means in the equalization pulse detection means comprises an exclusive OR gate for carrying out an exclusive OR logic of the external synchronous signal and the internal synchronous signal to generate the equalization pulse detection signal to the control signal generation means and the equalization period ending detection means.
The control signal generation means includes: a first flip flop where the equalization pulse detection signal received from the detection means is supplied as a clock signal and a power voltage is supplied as an input signal; an AND gate for carrying out an AND logic of an external reset signal and the internal synchronous signal to generate an output signal for clearing the first flip flop; and a second flip flop where an output signal of the first flip flop is supplied as a clock signal, the power supply is supplied as an input signal, the trigger signal received from the trigger signal generation means is supplied as a clear signal and the control signal is generated as an output signal to the output selection means and the equalization period ending detection means.
The trigger signal generation means includes: a third flip flop where the equalization period ending detection signal is supplied as a clock signal, the power supply is supplied as an input signal and the trigger signal is generated as an output signal to the second flip flop; and an NAND gate for carrying out an NAND logic of the internal synchronous signal and the control signal received from the control signal generation means to generate an output signal for clearing the third flip flop.
The output selection means comprises a multiplexer which receives an signal for masking the phase difference detection signal generated from the phase comparison and the phase difference detection signal as two input signals and provides the masking signal in the equalization period or the phase difference detection signal in the non-equalization period as the output signal of the phase difference detection circuit according to the control signal.
The equalization period ending detection means comprises a counter means for counting the master clock signal received from the PLL by a desired number to generate the equalization period ending detection signal. The counter means of the equalization period ending detection means includes a plurality of D filp flops connected in cascade for dividing the master clock signal by 512 to detect the equalization period ending detection signal, each of the D flip flops where an output signal inverted is fed back to an input signal. Each of the D flip flops where the equalization pulse detection signal received from the equalization pulse detection means is supplied as a clear signal, the control signal is supplied as an enable signal and the output signal inverted of the preceding D flip flop is supplied as a clock signal.
There is provided to a phase difference detection circuit of a phase locked loop (PLL) for a liquid crystal display, which compares a phase between an external synchronous signal and an internal synchronous signal from the PLL to generate a phase difference detection signal, comprising: a phase comparison means for comparing the phase between the external synchronous signal and the inter
Hyundai Electronics Industries Co,. Ltd.
Selitto Behr & Kim
Tse Young T.
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