Phase detector with frequency steering

Details Phase detector with frequency steering Phase detector with frequency steering

1998-11-06

2001-12-04

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S156000, C327S257000

Reexamination Certificate

active

06327319

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to phase detectors for phase locked loops and, more particularly to, a phase detector with frequency steering for phase locked loops.
BACKGROUND OF THE INVENTION
Generally, phase detectors for use in phase locked loops (PLL's) are known in the art. In a PLL, a phase detector compares the phase of the reference signal to the phase of a divided voltage controlled oscillator (VCO) signal. The output of the phase detector then drives a charge pump which in turn drives a loop filter followed by a VCO. The VCO produces the VCO signal which is divided by a loop divider to generate the divided VCO signal.
Three common types of phase detectors known in the art include an exclusive-OR phase detector, a tri-state phase detector and a dual state phase detector.
FIGS. 6-8
describe an exclusive-OR phase detector in accordance with the prior art.
FIGS. 9-13
describe a tri-state phase detector in accordance with the prior art.
FIGS. 14-21
describe a dual state phase detector in accordance with the prior art.
Turning first to the exclusive-OR phase detector,
FIG. 6
illustrates a block diagram of an exclusive-OR phase detector
600
in accordance with the prior art.
FIG. 7
illustrates a timing diagram
700
for the exclusive-OR phase detector
600
of
FIG. 6
in accordance with the prior art.
FIG. 8
illustrates a graph
800
depicting output voltage versus phase for the exclusive-OR phase detector
600
of
FIG. 6
in accordance with the prior art.
In
FIG. 6
, the exclusive-OR phase detector
600
has two input terminals and an output terminal. A first terminal receives a divided reference frequency signal
604
from a reference frequency divider (not shown). A second terminal receives a divided VCO frequency signal
606
from a loop divider (not shown). The output terminal produces a phase error signal
608
. Typically, the phase error signal is a voltage signal.
The exclusive-OR phase detector
600
operates according to a timing diagram
700
of the waveforms represented in FIG.
7
and according to the following truth table.
Source 1 (604)
Source 2 (606)
Output (608)
0
0
0
0
1
1
1
0
1
1
1
0
When the two sources produce signals
604
and
606
that are in phase, the output voltage
608
is at a logic zero level. When the two sources produce signals
604
and
606
that are 180 degrees out of phase, then the output voltage
608
is at a logic high level (typically, a logic supply voltage represented by Vcc). Any condition of phase shift between the logic zero level and the logic high level results in the output voltage
608
being averaged between the logic zero level and the logic high level. The output voltage
608
of the exclusive-OR phase detector
600
is filtered by a filter (not shown) to reduce the large variation between the logic zero level and the logic high level.
A graph
800
of the average output voltage
608
versus phase error for the exclusive-OR phase detector
600
is shown in FIG.
8
. In
FIG. 8
, a gain of the exclusive-OR phase detector
600
is represented as the slope of the average output voltage
608
(Vcc) versus phase. In
FIG. 8
, the slope is Vcc/phase volts per radian.
The exclusive-OR phase detector
600
has at least two disadvantages. First, the same output voltage is generated for positive and negative phase errors. Thus, to lock the PLL at zero phase error the exclusive-OR phase detector
600
needs to be modified. Second, output voltage
608
of the exclusive-OR phase detector
600
depends on the pulse width of the input pulses from the two input signals
604
and
606
. Thus, if one signal has narrow pulses and the other signal has wide pulses then the gain of the exclusive-OR phase detector
600
will be dramatically different.
Turning next to the tri-state phase detector,
FIG. 9
illustrates a block diagram of a tri-state phase detector
901
and a charge pump
903
in accordance with the prior art. The tri-state phase detector
901
is generally an improvement over the exclusive-OR phase detector
600
.
In
FIG. 9
, the tri-state phase detector
901
generally includes a first D-type flip flop
902
, a second D-type flip flop
904
, and an AND gate
906
. The first D-type flip flop
902
has a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal. The first terminal is coupled to a positive supply voltage
908
. The second terminal is coupled to receive a divided reference frequency signal
910
(Fref). The third terminal generates a first output signal
912
. The fourth terminal generates a second output signal
914
(i.e., the UP (up) signal). The fifth terminal is coupled to receive a reset signal
924
. The second D-type flip flop
904
has a first terminal, a second terminal, a third terminal, a fourth terminal and a fifth terminal. The first terminal is coupled to the positive supply voltage
916
. The second terminal is coupled to receive a divided VCO frequency signal
918
(Fvco). The third terminal generates a first output signal
920
. The fourth terminal generates a second output signal
922
(i.e., the DN (down) signal). The fifth terminal is coupled to receive the reset signal
924
.
In
FIG. 9
, the charge pump
903
generally includes a first current source
926
and a second current source
928
. The first current source
926
has a first terminal, a second terminal and a third terminal. The first terminal is coupled to the positive supply voltage
932
. The second terminal is coupled to receive the UP signal
914
from the first D-type flip flop
902
. The third terminal generates an output current signal
930
. The second current source
928
has a first terminal, a second terminal and a third terminal. The first terminal
932
is coupled to the third terminal of the first current source
926
and is operative to produce the output current signal
930
. The second terminal is coupled to receive the DN signal
922
from the second D-type flip flop
904
. The third terminal is coupled to a ground potential.
Generally, in operation of the tri-state phase detector
901
, a phase difference between Fref
910
and Fvco cause the UP signal
914
and the DN signal
922
of the tri-state phase detector
901
to vary. The UP signal
914
and the DN signal
922
of the tri-state phase detector
901
drive the two current sources
926
and
928
of the charge pump
903
which charge or discharge loop filter capacitors (not shown in
FIG. 9
) to form a voltage control for a VCO (not shown in
FIG. 9
) in a PLL (not shown in FIG.
9
).
Particularly, in operation of the tri-state phase detector
901
, consider the case where Fref
910
rises before Fvco
918
, wherein both of the D-type flip flops
902
and
904
are edge triggered. On the rising edge of Fref
910
, the first D-type flip flop
902
sets its first output signal
912
to a logic high and its second output signal
914
to a logic low. Both output signals
912
and
914
will remain in this state until Fvco
918
rises. When Fvco
918
rises then the second D-type flip flop
904
sets its first output signal
920
a logic high and its second output signal
922
to a logic low. The logic high of the first output signal
912
from the first D-type flip flop
902
and the logic high of the first output signal
920
from the second D-type flip flop
904
cause the AND gate
906
to generate the reset signal
924
at a logic high to reset both flip flops
902
and
904
. When this reset occurs the tri-state phase detector
901
returns to its initial state and is ready to receive another set of pulses from Fref
910
and Fvco
918
. This operation of the tri-state phase detector
901
causes the UP signal
914
will be low for a time which is equal to the delay between Fref
910
and Fvco
918
. The logic low pulse from the UP signal
914
drives the first current source
926
which charges the loop filter capacitors in the PLL to a higher voltage. Responsive to the higher voltage, the VCO in the PLL increases its frequency to cause a pulse of Fvco
918
to occur soo

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