Phase detector system with asynchronous output override

Details Phase detector system with asynchronous output override Phase detector system with asynchronous output override

2007-09-25

2007-09-25

Ha, Dac V. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S376000, C327S148000, C327S157000

Reexamination Certificate

active

10718206

ABSTRACT:
In one embodiment, the present invention provides a phase-locked loop comprising a charge-pump loop filter and a phase detector system. The charge-pump loop filter is configured to provide a control voltage having a voltage level based on a state of a first control signal and on a state of a second control signal. The phase detector system is configured to receive a first clock, a second clock, and a control signal defining a plurality of states including a first state and a second state. The phase detector system is further configured to provide the first control signal and the second control signal each having a state based on a phase difference between the first and second clocks when the control signal has the first state, and to provide the first control signal and second control signal each having a state asynchronously controlled by the control signal when the control signal has the second state.

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