Phase detector for a phase-locked loop

Details Phase detector for a phase-locked loop Phase detector for a phase-locked loop

2007-07-10

2007-07-10

Tran, Khai (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000

Reexamination Certificate

active

10049592

ABSTRACT:
A phased-locked loop phase detector for digital input signals in which digital summed value for a particular number of bits is equal to zero. Sampled and digitized data comprising a delay stage for delaying the data signal by a one or more sampling clock period is supplied to the phase detector as an input signal. The delayed data signal and the undelayed data signal are then supplied to a subtraction stage. The difference between the two input values is formed in this subtraction stage. The processing stage assigns one of a plurality of possible values to the respective differential value. The full differential value range is subdivided in a number of sub-ranges corresponding to the plurality of possible values. All differential values in one sub-range are assigned the same output value. The output of the subtraction stage is supplied to a filter/control stage.

REFERENCES:
patent: 5027085 (1991-06-01), Devito
patent: 5311178 (1994-05-01), Pan et al.
patent: 5452326 (1995-09-01), Tanaka
patent: 5592125 (1997-01-01), Williams
patent: 5778032 (1998-07-01), Tanaka et al.
patent: 5986834 (1999-11-01), Colineau et al.
patent: 6118606 (2000-09-01), Sasaki
patent: 6483871 (2002-11-01), Dawe
patent: 0549412 (1993-06-01), None
Patent Abstracts of Japan, vol. 1996, No. 06, Jun. 28, 1996 & JP 8-031110, published Feb. 2, 1996.

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