Phase detector arrangement

Details Phase detector arrangement Phase detector arrangement

1998-05-14

2001-11-27

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000, C327S147000, C327S157000, C331S025000

Reexamination Certificate

active

06324236

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a phase detector arrangement for use in a phase locked loop circuit, for recovery of clock and data pulses from a data stream which comprises Return to Zero RZ signals comprising digital data, said arrangement comprising a comparator, a phase detector, a loop filter and a voltage controlled oscillator, wherein the phase detector comprises a phase position indicator which is activated by each incoming data pulse in the output line of the comparator, said phase position indicator being adapted to control the voltage controlled oscillator in relation to both edges of each data pulse, for clocking data synchronously with said data pulse. The present invention also relates to a method for recovery of clock and data pulses from a received data stream which comprises Return to Zero RZ signals comprising digital data and is received via a comparator, said arrangement comprising a phase detector, a loop filter and a voltage controlled oscillator, wherein the data pulses in the or each output line of the comparator are monitored and the voltage controlled oscillator is controlled in relation to both edges of each data pulse, for clocking synchronously with said data pulse.
In the field of single line digital communication, the recovery of clock and data pulses from a received RZ-signal can be accomplished by means of a tank circuit. A tank circuit comprises LC-filters that filters out the clock frequency from the timing contents of the input signal plus a sine/square wave converter that converts it into a square wave digital clock signal.
These solutions are cost-efficient and are often applied to traditional PDH-equipment. One peculiarity with tank circuits is that the clock signal disappears about 10-20 pulses after that the input signal has disappeared. While the tank circuits are capable to withstand a tremendously jittered input signal, they are not good at dampening jitter and they are not good at enduring noise. There is also a risk of producing jitter within said circuits.
Another solution is to use a phase locked loop circuit for clock and data recovery. This type of circuit is more flexible and may for example be made more narrow-banded than tank circuit solutions, and is therefore able to damp jitter more efficiently and is less sensitive to noise and maintains the clock signal even if the input signal is missing. Commonly used phase detectors, for example of the type Phase-Frequency comparators, Exclusive-or or Set-Reset flip-flop, all being present within the circuit 74HC4046, require input signals continuously each period from signal and reference in order to be able to detect the phase position correctly. These phase detectors can not work upon RZ signals.
In order to be able to detect the phase position of a RZ signal, for example of any of the types B3ZS, HDB-3, AMI or RZ, and the clock with which the data should be recovered, the comparison must be made exclusively with those parts of the signal which provide a pulse of the type RZ. It would be possible to measure the time it takes from the front edge of the RZ-signal to the desired clock-edge. This may be accomplished analogously or digitally by means of digital counters. One drawback with counters is that the clock frequency to the counters must be considerably higher than that of the clock and data that is to be recovered, if a high phase position accuracy is desirable. This may be a problem at high frequencies, among other with regard to technology, power consumption and cost.
SUMMARY
What is needed is therefore a cost-efficient phase detector arrangement which is able to operate at high frequencies with low power.
According to the invention, this is accomplished by connecting the phase position indicator output in series via a resistor to an earth-connected capacitor, for integration of the output signal with reference to the duration of each data pulse to a mean value which corresponds to the phase position between the data pulse and the clock signal.
In a particular embodiment of the invention, the output line of the phase detector is connected to the voltage controlled oscillator via the loop filter.
The comparator may be provided with two output lines and the phase detector may comprise two phase position indicators, wherein either one or the other indicator is activated for each incoming data pulse in the output lines of the comparator. These phase position indicators may be mutually connected to a connection point and from said point connected in series via the resistor to the earth-connected capacitor.
The clock signal of the voltage controlled oscillator may be used as input to the phase detector.
The voltage over the capacitor may be used for controlling the output phase of the voltage controlled oscillator.
The or each phase position indicator may be a tristate buffer. Alternatively, each phase position indicator may be an analogue switch.
The arrangement according to the invention may be used in a telecommunication system.
The method according to the invention comprises the steps of integrating the input signal controlled by or each output line with reference to the duration of each pulse to a mean value which corresponds to the phase position between the data pulse and the clock signal.
The clock signal may be used to be switched out as phase position pulses.


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