Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-02-25
2003-07-01
Corrielus, Jean (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C360S051000
Reexamination Certificate
active
06587529
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for estimating phase error, for example, of a timing recovery loop. More specifically, a preferred embodiment relates to efficiently selecting the starting phase for a timing recovery process in a sampled data detection system, such as a PRML or EPRML channel in a magnetic recording system.
BACKGROUND
Digital mass data storage devices such as a disk drive record digital sequences onto media and retrieve them from an analog signal, unfortunately corrupted by noise from various sources. It is desired to achieve the highest recording density per unit area while attaining an acceptable probability of error between the signal recorded and that retrieved. To achieve this goal, a disk drive's read channel uses equalization and coding prior to processing in a digital signal processor. One solution is to use run-length limited (RLL) codes with a RLL encoder and decoder.
Digital mass data storage devices use RLL codes, when applied to data only, to improve signal-to-noise ratio (SNR) or to implement frequent updates to the timing recovery and automatic gain control loops, or both. The RLL codes use two parameters, d and k, controlling the minimum and maximum number of symbol intervals between transitions in the input signal, respectively. For a given d, the RLL code dictates at least “d+1”, and at most “k+1”, symbol intervals between transitions. Conventionally used codes are those with (d, k) constraints of (1, 7) and (2,7), generally used with peak detection methods.
These asynchronous methods detect single pulses. The “k” constraint insures that a non-zero channel output is produced with some minimum frequency to maintain robust operation of timing recovery and AGC loops. The “d” constraint insures acceptable SNR with peak detection.
Conventional methods for estimating the initial phase error for ZPR have been applied to determine “zero-crossings” of analog, i.e., continuous, time signals. Of course, this is inappropriate for handling discrete, or digital, pulses.
Some conventional disk drives, for example, use continuous time peak detection designs to recover digital data written as a series of magnetic transitions on a recording surface of a rotating magnetic disk. A voltage controlled oscillator (VCO) uses an “Enable” command for controlled starting and stopping of the oscillator. When the “Enable” command is asserted, the VCO begins oscillating in a known state. The rising edges of the clock's transition occur at a fixed delay interval after “Enable” is asserted.
In turn, “zero phase restart” (ZPR), also sometimes referred to as zero phase start, senses a logic transition of a read gate control signal (“Rd Gate”) from inactive to active, and disables the VCO. Upon arrival of a subsequent “transition edge” at the ZPR logic, “Enable” is reasserted and the timing control circuit VCO is restarted. A timing delay block compensates for the delays associated with detection and restart, which results in the next transition edge and the first clock output coinciding at the input to the phase-frequency detector. Starting phase error,
is brought near zero while PLL acquisition time is reduced.
One effect that limits the recording density in mass data storage systems is intersymbol interference (ISI). ISI is endemic to the band-limited nature of the head/media combination and results in overlapping responses. That is, at a given time, the output signal contains the response due to the input signal and the responses from some previously recorded symbols. This overlap increases as recording density or disk rotation speed is increased, yielding overlap patterns that are generally very difficult to decode.
To reduce the complexity required to decode, the readback signal in the read channel is first equalized to a prescribed partial response (PR) signal. PR signals permit a controlled overlap of responses in the output signal. A priori knowledge of the “controlled overlap” significantly reduces the complexity of the required detector, compared to that required for an unequalized signal.
One commonly-used PR target signal in digital magnetic recording systems is characterized by the transfer function P(D)=1−D
2
, where D is the transform of the unit symbol delay operation. This PR signal is commonly referred to as a “Class IV PR” or “PR4.” The noise-free output response at a suitably prescribed sampling instant for PR4 is given by
Y
(
nT
)=
a
(
nT
)−
a
[(
n
−2)
T]
(1)
where:
n
=
2
,
3
,
…
a
(
nT
)
=
the
input
symbol
at
time
instant
nT
,
normally
picked
from
a
binary
alphabet
,
{
0
,
1
}
or
{
1
,
-
1
}
.
That is, the output sample at time instant, nT, involves the overlap of two input symbols, a(nT) and a[(n−2)T].
The equalized signal is then detected using a sequence detector such as a Viterbi Detector (based on the Viterbi Algorithm). This combination of PR4 and Viterbi detection is commonly referred to as “PRML” for “partial response maximum-likelihood.”
To increase storage density and throughput rate, sampling techniques, such as the above Partial Response (PR) signaling and Maximum Likelihood (ML) sequence detection are used.
The choice of the PR target signal is dictated by the linear density of the recording (as well as additional functions that may be required of the system). A single system may require two different PR target signals, e.g., PR4 and EPR4. Many PR targets exist for magnetic recording and are now commonly referred to as the “Extended Class IV” family of PR signals. The Extended Class IV family of PR signals is defined by the polynomials P(D))=(1−D)(1+D)
n
, where n is a positive integer. Note that n=1 yields the standard PR4 signal; while n=2 yields EPR4; and n=3 yields E
2
PR4, etc.
Correct operation of any PRML system depends on sampling the readback signal synchronously. Even small time shifts from the correct sampling instant act to distort the sample values. To maintain proper timing of the read data, a timing recovery circuit, often a PLL, is used to adjust the phase of a VCO based on the phase error,
determined by a digital phase error detector receiving input from an analog-to-digital converter (ADC).
During acquisition, the phase error,
is defined as being zero when the rising edge of the clock signal is aligned with the ideal sampling instances of the input signal. A non-zero phase error,
causes the error detector to send a signal to a loop filter that outputs a signal proportional to the phase error. This signal shifts the instantaneous frequency of the VCO in order to subsequently match the phase of the input signal.
A PRML read channel uses ML detectors to “read” data based on sampled sequences of an analog waveform read from a disk, rather than by analyzing a single peak as in conventional peak detection. These samples are obtained by using an ADC that samples and quantizes the read waveform at predetermined sampling intervals. The intervals are controlled by a clock synchronizing the ADC and the incoming signal. The clock also must be phase aligned to the incoming signal.
To achieve proper timing and phase synchronization, a conventional PRML read channel uses a timing control circuit to acquire and lock frequency and phase synchronization. The timing control circuit uses a PLL circuit to generate a phase-coherent clock so that data samples may be taken at predetermined locations along the input signal. It is necessary to first lock the PLL circuit to a reference so that the required sampling frequency can be acquired and tracked.
A phase detector processes the signal samples to calculate a phase error,
between the actual and desired signals. A compensation to this phase error is used to adjust the sampling fre
Spagna Fulvio
Staszewski Robert B.
Brady W. James
Corrielus Jean
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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